From: Dmitry Baryshkov dmitry.baryshkov@linaro.org
[ Upstream commit e93eee524bb78f3ee4b78654d0083382f98b3d23 ]
In case of ACTIVE CTLs, a single CTL is being used for flushing all INTF blocks. Don't skip programming the CTL on those targets.
Tested-by: Neil Armstrong neil.armstrong@linaro.org # on SM8550-QRD Signed-off-by: Dmitry Baryshkov dmitry.baryshkov@linaro.org Patchwork: https://patchwork.freedesktop.org/patch/641585/ Link: https://lore.kernel.org/r/20250307-dpu-active-ctl-v3-5-5d20655f10ca@linaro.o... Signed-off-by: Dmitry Baryshkov dmitry.baryshkov@oss.qualcomm.com Signed-off-by: Sasha Levin sashal@kernel.org ---
**YES** This commit should be backported to stable kernel trees. ## Analysis: **1. Clear Bug Fix Nature:** The commit fixes a functional bug where CTL programming was being incorrectly skipped on ACTIVE CTL configurations. The commit message explicitly states "Don't skip programming the CTL on those targets" indicating incorrect behavior was occurring. **2. Small and Contained Change:** The change is minimal - it modifies only the `dpu_encoder_phys_vid_needs_single_flush()` function by adding a single condition check: ```c - return phys_enc->split_role != ENC_ROLE_SOLO; + return !(phys_enc->hw_ctl->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) && + phys_enc->split_role != ENC_ROLE_SOLO; ``` **3. Hardware-Specific Fix:** The fix addresses a specific hardware configuration issue for devices with `DPU_CTL_ACTIVE_CFG` feature. From examining the kernel code, this affects multiple SoCs including SM8150, SM8250, SM6150, SC7180, and others - making it a widely impacting fix. **4. Clear Functional Impact:** - **Before**: On ACTIVE CTL targets, the function incorrectly returned true for split configurations, causing CTL programming to be skipped - **After**: On ACTIVE CTL targets, it returns false, ensuring proper CTL programming occurs - **Effect**: Ensures display pipeline functions correctly on affected hardware **5. Tested Change:** The commit includes "Tested-by: Neil Armstrong neil.armstrong@linaro.org # on SM8550-QRD" indicating real hardware testing was performed. **6. Matches Successful Backport Pattern:** This commit closely matches the pattern of Similar Commits #1, #2, and #4 (all marked YES): - Small, targeted fix (line 377 in `dpu_encoder_phys_vid.c:377`) - Addresses incorrect hardware behavior - Has clear before/after functional difference - Affects critical graphics subsystem functionality **7. Risk Assessment:** - **Low regression risk**: The change only affects the specific condition logic - **Targeted scope**: Only impacts ACTIVE CTL configurations - **Conservative fix**: Makes the logic more restrictive (requires both conditions to skip programming) This is a clear hardware bug fix that prevents display issues on affected SoCs and follows the stable tree criteria for important bugfixes with minimal regression risk.
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 33880f66625e6..f9da379999467 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -353,7 +353,8 @@ static void dpu_encoder_phys_vid_underrun_irq(void *arg, int irq_idx) static bool dpu_encoder_phys_vid_needs_single_flush( struct dpu_encoder_phys *phys_enc) { - return phys_enc->split_role != ENC_ROLE_SOLO; + return !(phys_enc->hw_ctl->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) && + phys_enc->split_role != ENC_ROLE_SOLO; }
static void _dpu_encoder_phys_vid_setup_irq_hw_idx(