The patch below does not apply to the 6.1-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to stable@vger.kernel.org.
To reproduce the conflict and resubmit, you may use the following commands:
git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.1.y git checkout FETCH_HEAD git cherry-pick -x 9749a42db74c3400e0526d9a39fa0324abfd0d66 # <resolve conflicts, build, test, etc.> git commit -s git send-email --to 'stable@vger.kernel.org' --in-reply-to '2023072138-henchman-crusader-a6ce@gregkh' --subject-prefix 'PATCH 6.1.y' HEAD^..
Possible dependencies:
9749a42db74c ("drm/amd/display: Change default Z8 watermark values") 9b0f51e8449f ("drm/amd/display: Update Z8 SR exit/enter latencies") fa24e116f1ce ("drm/amd/display: Update Z8 watermarks for DCN314")
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From 9749a42db74c3400e0526d9a39fa0324abfd0d66 Mon Sep 17 00:00:00 2001 From: Leo Chen sancchen@amd.com Date: Thu, 13 Apr 2023 17:34:24 -0400 Subject: [PATCH] drm/amd/display: Change default Z8 watermark values
[Why & How] Previous Z8 watermark values were causing flickering and OTC underflow. Updating Z8 watermark values based on the measurement.
Reviewed-by: Nicholas Kazlauskas Nicholas.Kazlauskas@amd.com Cc: Mario Limonciello mario.limonciello@amd.com Cc: Alex Deucher alexander.deucher@amd.com Cc: stable@vger.kernel.org Acked-by: Alan Liu HaoPing.Liu@amd.com Signed-off-by: Leo Chen sancchen@amd.com Signed-off-by: Alex Deucher alexander.deucher@amd.com
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c index 19370b872a91..1d00eb9e73c6 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c @@ -149,8 +149,8 @@ static struct _vcs_dpi_soc_bounding_box_st dcn3_14_soc = { .num_states = 5, .sr_exit_time_us = 16.5, .sr_enter_plus_exit_time_us = 18.5, - .sr_exit_z8_time_us = 210.0, - .sr_enter_plus_exit_z8_time_us = 310.0, + .sr_exit_z8_time_us = 268.0, + .sr_enter_plus_exit_z8_time_us = 393.0, .writeback_latency_us = 12.0, .dram_channel_width_bytes = 4, .round_trip_ping_latency_dcfclk_cycles = 106,