From: Laxman Dewangan ldewangan@nvidia.com
commit b22ef2a0979f2b91cfeeabb086e4d665183a93a1 upstream.
The pincontrol registers of Tegra chips has multiple filed per registers. There is two type of registers mux and drive. All configurations belongs to one of these registers.
If any configurations are supported then <config>_bit is set to bit position of these registers otherwise -1 to not support it. The member is defined as s32 <config>_bit:6;
So if config is not supported ifor given SoC then it is set to -1 in soc pinmmux table. In common driver code, to find out that given config is supported or not, it is checked as:
s8 bit = <config>_bit; if (bit > 31) { /* Not supported config */ }
But in this case, bit is s8 and hence for non supporting it is -1.
Correct the check as: if (bit < 0) { /* Not supported config */ }
Fixes: e4c02dced975cb ("pinctrl: tegra: use signed bitfields for optional fields") Signed-off-by: Laxman Dewangan ldewangan@nvidia.com Acked-by: Stephen Warren swarren@nvidia.com Signed-off-by: Linus Walleij linus.walleij@linaro.org Signed-off-by: Greg Kroah-Hartman gregkh@linuxfoundation.org
--- drivers/pinctrl/pinctrl-tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/pinctrl/pinctrl-tegra.c +++ b/drivers/pinctrl/pinctrl-tegra.c @@ -418,7 +418,7 @@ static int tegra_pinconf_reg(struct tegr return -ENOTSUPP; }
- if (*reg < 0 || *bit > 31) { + if (*reg < 0 || *bit < 0) { if (report_err) { const char *prop = "unknown"; int i;