On 20.07.2023 23:07, Andi Shyti wrote:
Just a trivial refactoring for reducing the number of code duplicate. This will come at handy in the next commits.
Signed-off-by: Andi Shyti andi.shyti@linux.intel.com Cc: stable@vger.kernel.org # v5.8+
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 44 +++++++++++++----------- 1 file changed, 23 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c index 9d050b9a19194..202d6ff8b5264 100644 --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c @@ -177,23 +177,31 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv return cs; } +static u32 *intel_emit_pipe_control_cs(struct i915_request *rq, u32 bit_group_0,
u32 bit_group_1, u32 offset)
s/intel/gen12/
but this and few other issues were raised already by Matt in v6.
Regards Andrzej
+{
- u32 *cs;
- cs = intel_ring_begin(rq, 6);
- if (IS_ERR(cs))
return cs;- cs = gen12_emit_pipe_control(cs, bit_group_0, bit_group_1,
LRC_PPHWSP_SCRATCH_ADDR);- intel_ring_advance(rq, cs);
- return cs;
+}
- static int mtl_dummy_pipe_control(struct i915_request *rq) { /* Wa_14016712196 */ if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {u32 *cs;/* dummy PIPE_CONTROL + depth flush */cs = intel_ring_begin(rq, 6);if (IS_ERR(cs))return PTR_ERR(cs);cs = gen12_emit_pipe_control(cs,0,PIPE_CONTROL_DEPTH_CACHE_FLUSH,LRC_PPHWSP_SCRATCH_ADDR);intel_ring_advance(rq, cs);- }
IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0))intel_emit_pipe_control_cs(rq,0,PIPE_CONTROL_DEPTH_CACHE_FLUSH,LRC_PPHWSP_SCRATCH_ADDR);return 0; } @@ -210,7 +218,6 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) u32 bit_group_0 = 0; u32 bit_group_1 = 0; int err;
u32 *cs;err = mtl_dummy_pipe_control(rq); if (err) @@ -244,13 +251,8 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) else if (engine->class == COMPUTE_CLASS) bit_group_1 &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
cs = intel_ring_begin(rq, 6);if (IS_ERR(cs))return PTR_ERR(cs);cs = gen12_emit_pipe_control(cs, bit_group_0, bit_group_1,LRC_PPHWSP_SCRATCH_ADDR);intel_ring_advance(rq, cs);
intel_emit_pipe_control_cs(rq, bit_group_0, bit_group_1,LRC_PPHWSP_SCRATCH_ADDR);if (mode & EMIT_INVALIDATE) {