6.11-stable review patch. If anyone has any objections, please let me know.
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From: Andrew Jones ajones@ventanamicro.com
[ Upstream commit 4a1361e9a5c5dbb5c9f647762ae0cb1a605101fa ]
The "per-CPU IDs ... at base ..." info log is outputting a physical address, not a PPN.
Fixes: 027e125acdba ("irqchip/riscv-imsic: Add device MSI domain support for platform devices") Signed-off-by: Andrew Jones ajones@ventanamicro.com Signed-off-by: Thomas Gleixner tglx@linutronix.de Reviewed-by: Anup Patel anup@brainfault.org Link: https://lore.kernel.org/all/20240909085610.46625-2-ajones@ventanamicro.com Signed-off-by: Sasha Levin sashal@kernel.org --- drivers/irqchip/irq-riscv-imsic-platform.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/irq-riscv-imsic-platform.c index 11723a763c102..c5ec66e0bfd33 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -340,7 +340,7 @@ int imsic_irqdomain_init(void) imsic->fwnode, global->hart_index_bits, global->guest_index_bits); pr_info("%pfwP: group-index-bits: %d, group-index-shift: %d\n", imsic->fwnode, global->group_index_bits, global->group_index_shift); - pr_info("%pfwP: per-CPU IDs %d at base PPN %pa\n", + pr_info("%pfwP: per-CPU IDs %d at base address %pa\n", imsic->fwnode, global->nr_ids, &global->base_addr); pr_info("%pfwP: total %d interrupts available\n", imsic->fwnode, num_possible_cpus() * (global->nr_ids - 1));