On Tue, Jan 05, 2021 at 08:20:51AM -0800, Andy Lutomirski wrote:
Interestingly, the architecture recently added a control bit to remove this synchronisation from exception return, so if we set that then we'd have a problem with SYNC_CORE and adding an ISB would be necessary (and we could probable then make kernel->kernel returns cheaper, but I suspect we're relying on this implicit synchronisation in other places too).Is ISB just a context synchronization event or does it do more?
IIRC it just the instruction sync (like power ISYNC).
On x86, it’s very hard to tell that MFENCE does any more than LOCK, but it’s much slower. And we have LFENCE, which, as documented, doesn’t appear to have any semantics at all. (Or at least it didn’t before Spectre.)
AFAIU MFENCE is a completion barrier, while LOCK prefix is not. A bit like ARM's DSB vs DMB.
It is for this reason that mb() is still MFENCE, while our smp_mb() is a LOCK prefixed NO-OP.
And yes, LFENCE used to be poorly defined and it was sometimes understood to be a completion barrier relative to prior LOADs, while it is now a completion barrier for any prior instruction, and really should be renamed to IFENCE.