On Fri, 24 Feb 2023 13:30:45 +0530, Manivannan Sadhasivam wrote:
The iommu mask should be 0x3f as per Qualcomm internal documentation. Without the correct mask, the PCIe transactions from the endpoint will result in SMMU faults. Hence, fix it!
Applied, thanks!
[1/1] arm64: dts: qcom: sm8150: Fix the iommu mask used for PCIe controllers commit: 672a58fc7c477e59981653a11241566870fff852
Best regards,