Hi, Marc,
On Thu, Sep 10, 2020 at 6:10 PM Marc Zyngier maz@kernel.org wrote:
On 2020-09-09 05:09, Huacai Chen wrote:
Modernized Loongson64 uses a hierarchical organization for interrupt controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) is not enough to represent all interrupts, so let's increase NR_IRQS to 320.
Cc: stable@vger.kernel.org Signed-off-by: Huacai Chen chenhc@lemote.com
arch/mips/include/asm/mach-loongson64/irq.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h index f5e362f7..0da3017 100644 --- a/arch/mips/include/asm/mach-loongson64/irq.h +++ b/arch/mips/include/asm/mach-loongson64/irq.h @@ -7,7 +7,7 @@ /* cpu core interrupt numbers */ #define NR_IRQS_LEGACY 16 #define NR_MIPS_CPU_IRQS 8 -#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) +#define NR_IRQS 320
#define MIPS_CPU_IRQ_BASE NR_IRQS_LEGACY
Why are you hardcoding a random value instead of bumping the constant in NR_IRQS?
Because INTCs can organized in many kinds of hierarchy, we cannot use constants to define a accurate value, but 320 is big enough.
Huacai
M.-- Jazz is not dead. It just smells funny...