On Fri, Jan 10, 2025 at 11:10 PM Prabhakar prabhakar.csengg@gmail.com wrote:
From: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com
The PFC_MASK value for the PFC_mx register was previously hardcoded as `0x07`, which is correct for SoCs in the RZ/G2L family but insufficient for RZ/V2H and RZ/G3E, where the mask value should be `0x0f`. This discrepancy caused incorrect PFC register configurations on RZ/V2H and RZ/G3E SoCs.
On the RZ/G2L, the PFC_mx bitfields are also 4 bits wide, with bit 4 marked as reserved. The reserved bits are documented to read as zero and be ignored when written. Updating the PFC_MASK definition from `0x07` to `0x0f` ensures compatibility with both SoC families while maintaining correct behavior on RZ/G2L.
Fixes: 9bd95ac86e70 ("pinctrl: renesas: rzg2l: Add support for RZ/V2H SoC") Cc: stable@vger.kernel.org Reported-by: Hien Huynh hien.huynh.px@renesas.com Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com
v1->v2
- Dropped SoC specific configuration
Reviewed-by: Geert Uytterhoeven geert+renesas@glider.be i.e. will queue in renesas-pinctrl for v6.14, as it is a fix.
Gr{oetje,eeting}s,
Geert