On Thu, 12 Jun 2025 00:47:46 +0300, Cristian Ciocaltea wrote:
Since commit c871a311edf0 ("phy: rockchip: samsung-hdptx: Setup TMDS char rate via phy_configure_opts_hdmi"), the workaround of passing the PHY rate from DW HDMI QP bridge driver via phy_set_bus_width() became partially broken, unless the rate adjustment is done as with RK3588, i.e. by CCF from VOP2.
Attempting to fix this up at PHY level would not only introduce additional hacks, but it would also fail to adequately resolve the display issues that are a consequence of the system CRU limitations.
[...]
Applied, thanks!
[2/3] arm64: dts: rockchip: Enable HDMI PHY clk provider on rk3576 commit: aba7987a536cee67fb0cb724099096fd8f8f5350 [3/3] arm64: dts: rockchip: Add HDMI PHY PLL clock source to VOP2 on rk3576 commit: 4ab8b8ac952fb08d03655e1da0cfee07589e428f
Best regards,