Hello Christian,
On Fri, Oct 02, 2020 at 10:01:30AM +0200, Christian Eggers wrote:
On Friday, 25 September 2020, 10:11:01 CEST, Uwe Kleine-König wrote:
On Thu, Sep 17, 2020 at 04:13:50PM +0200, Christian Eggers wrote: IMHO the intention here (and also what happens on i.MX) is that exactly the AL interrupt pending bit should be cleared and the IF irq is supposed to be untouched.
Yes.
Given there are only two irq flags in the I2SR register (which is called IBSR on Vybrid) ...
Vybrid:
+-------+-----+------+-----+------+-----+-----+------+------+ | BIT | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +-------+-----+------+-----+------+-----+-----+------+------+ | READ | TCF | IAAS | IBB | IBAL | 0 | SRW | IBIF | RXAK | +-------+-----+------+-----+------+-----+-----+------+------+ | WRITE | - | - | - | W1C | - | - | W1C | - | +-------+-----+------+-----+-^^^--+-----+-----+-^^^--+------+
i.MX:
+-------+-----+------+-----+------+-----+-----+------+------+ | BIT | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +-------+-----+------+-----+------+-----+-----+------+------+ | READ | ICF | IAAS | IBB | IAL | 0 | SRW | IIF | RXAK | +-------+-----+------+-----+------+-----+-----+------+------+ | WRITE | - | - | - | W0C | - | - | W0C | - | +-------+-----+------+-----+-^^^--+-----+-----+-^^^--+------+
... the status quo (i.e. without your patch) is:
On i.MX IAL is cleared
Yes
On Vybrid IIF (which is called IBIF there) is cleared.
If IBIF is set, then it's cleared (probably by accident). But in the "if (temp & I2SR_IAL)" condition, I focus on the IBAL flag, not IBIF.
With your patch we get:
On i.MX IAL is cleared
Yes
On Vybrid both IIF (aka IBIF) and IAL (aka IBAL) are cleared.
Agree. IBAL is cleared by intention, IBIF by accident (if set). Do you see any problem if IBIF is also cleared?
Yes. If there is a real problem I'm not sure, but it's enough of an issue that there are possible side effects on Vybrid. I refuse to think about real problems given that it is so easy to make it right.
To get it right for both SoC types you have to do (e.g.):
temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ I2SR_IAL;Sorry, even if this is correct, it looks hard to understand for me.
Maybe a comment would be appropriate, something like:
/* * i2sr_clr_opcode is the value to clear all interrupts. Here we * want to clear no irq but I2SR_IAL, so we write * ~i2sr_clr_opcode with just the I2SR_IAL bit toggled. */
Maybe put this comment together with the code in a new function to have it only once.
(and in i2c_imx_isr() the same using I2SR_IIF instead of I2SR_IAL because there currently IAL might be cleared by mistake on Vybrid).
I considered creating a patch, but as I don't have a Vybrid on my desk and on i.MX there is no change, I let you do this.
I also don't own a Vybrid system. I consider my patch correct in terms of clearing the IBAL flag (which was wrong before). Additional work may be useful for NOT clearing the other status flag. I also would like to keep this task for somebody who owns a Vybrid system. But the other patches in this series fixes some more important problems, so maybe you could give your acknowledge anyhow.
No, please don't replace one bug found by another (now) known bug. Still more given that the newly introduced bug is much harder to trigger and debug.
Best regards Uwe