From: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org
[ Upstream commit b63f008f395ca5f6bc89123db97440bdc19981c4 ]
According to Hardware Programming Guide for DSI PHY, the retime buffer resync should be done after PLL clock users (byte_clk and intf_byte_clk) are enabled. Downstream also does it as part of configuring the PLL.
Driver was only turning off the resync FIFO buffer, but never bringing it on again.
Reviewed-by: Dmitry Baryshkov dmitry.baryshkov@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org Patchwork: https://patchwork.freedesktop.org/patch/657823/ Link: https://lore.kernel.org/r/20250610-b4-sm8750-display-v6-6-ee633e3ddbff@linar... Signed-off-by: Dmitry Baryshkov dmitry.baryshkov@oss.qualcomm.com Signed-off-by: Sasha Levin sashal@kernel.org ---
LLM Generated explanations, may be completely bogus:
YES
- What it fixes - The 7nm DSI PHY driver turns off the retime/resync buffer early in bring-up but never turns it back on. See the existing “turn off resync FIFO” write in `drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c:1105` where it writes `0x00` to `REG_DSI_7nm_PHY_CMN_RBUF_CTRL`. Without re-enabling, the data path can be misaligned after PLL enable, which can cause link bring-up glitches or unstable output. The commit aligns with the Hardware Programming Guide: resync must be toggled after enabling the PLL clock users.
- What the change does - Adds enabling of the resync buffer immediately after enabling the global clock in the VCO prepare path: - `drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c:534` writes `0x1` to `REG_DSI_7nm_PHY_CMN_RBUF_CTRL` for the master PHY. - `drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c:536` does the same for the bonded slave PHY. - This pairs correctly with: - The earlier “off” write in init (`drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c:1105`) and - The disable path write to `0` in `dsi_pll_disable_sub()` (`drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c:544`). - The enable occurs after global clock enable in `dsi_pll_7nm_vco_prepare()` where `dsi_pll_enable_global_clk()` is called (visible in the same function), matching the prescribed sequence “after PLL clock users are enabled.”
- Evidence of correctness and low risk - The 10nm PHY already follows this exact pattern: enable RBUF after enabling global clock, disable it on unprepare. See: - Enable: `drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c:373` and `:375` - Disable: `drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c:383` - This parity strongly suggests the 7nm omission was a bug rather than an intentional difference. - The change is minimal, localized to the 7nm PHY VCO prepare path. No API or architectural changes; only two writes added and perfectly mirrored by existing disable writes. - The sequence is safe: it enables the resync only after clocks are enabled, matching the hardware programming guide and downstream practice; it also handles bonded PHY (slave) consistently.
- Stable backport criteria - Fixes a real, user-visible bug (display instability or bring-up issues on affected Qualcomm 7nm DSI PHYs). - Small and contained change with minimal regression risk. - No new features or architectural churn; confined to the msm DRM DSI PHY subsystem. - Mirrors a proven sequence present in the 10nm driver, improving confidence.
Given the above, this is a solid bug fix with low risk and clear benefit and should be backported to stable trees that include the 7nm DSI PHY driver.
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index 8c98f91a5930c..6b765f3fd529a 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -491,6 +491,10 @@ static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw) if (pll_7nm->slave) dsi_pll_enable_global_clk(pll_7nm->slave);
+ writel(0x1, pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL); + if (pll_7nm->slave) + writel(0x1, pll_7nm->slave->phy->base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL); + error: return rc; }