11 Apr
2019
11 Apr
'19
8:14 p.m.
Quoting Nicolas Boichat (2019-03-07 22:20:27)
On Tue, Mar 5, 2019 at 1:06 PM Weiyi Lu weiyi.lu@mediatek.com wrote:
From: Owen Chen owen.chen@mediatek.com
- pcwibits: The integer bits of pcw for plls is extend to 8 bits, add a variable to indicate this change and backward-compatible.
- fmin: The pll freqency lower-bound is vary from 1GMhz to
Minor nit: frequency (Stephen I guess you could fix that when applying...)
What's a 1GMhz? Anyway, fixed the typo.