Hello Robin,
On 2024-09-26 11:24, Robin Murphy wrote:
On 2024-09-26 8:49 am, Dragan Simic wrote:
Move the "l3_cache" node under the "cpus" node in the dtsi file for Rockchip RK356x SoCs. There's no need for this cache node to be at the higher level.
Except it does arguably represent the physical topology - the L3 cache doesn't belong to the CPUs, it belongs to the DSU, which very much is "outside" the CPUs.
That's a very good point, thanks! I knew there must have been a very good reason why I placed the L3 cache outside the CPUs originally, in the commit 8612169a05c5 referenced below, but I also somehow managed to forget that reason for a moment. :)
Let's drop this patch, and I'll submit another patch for the RK3588 SoC dtsi files that moves the L3 cache outside the CPUs, to reflect the physical topology better.
Fixes: 8612169a05c5 ("arm64: dts: rockchip: Add cache information to the SoC dtsi for RK356x") Cc: stable@vger.kernel.org Signed-off-by: Dragan Simic dsimic@manjaro.org
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 4690be841a1c..9f7136e5d553 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -113,19 +113,19 @@ cpu3: cpu@300 { d-cache-sets = <128>; next-level-cache = <&l3_cache>; };
- };
- /*
* There are no private per-core L2 caches, but only the* L3 cache that appears to the CPU cores as L2 caches*/- l3_cache: l3-cache {
compatible = "cache";cache-level = <2>;cache-unified;cache-size = <0x80000>;cache-line-size = <64>;cache-sets = <512>;
/** There are no private per-core L2 caches, but only the* L3 cache that appears to the CPU cores as L2 caches*/l3_cache: l3-cache {compatible = "cache";cache-level = <2>;cache-unified;cache-size = <0x80000>;cache-line-size = <64>;cache-sets = <512>;};
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