6.17-stable review patch. If anyone has any objections, please let me know.
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From: Quanyang Wang quanyang.wang@windriver.com
[ Upstream commit 0e3f9140ad04dca9a6a93dd6a6decdc53fd665ca ]
When secure-boot mode of bootloader is enabled, the registers of coresight are not permitted to access that's why disable it by default.
Signed-off-by: Quanyang Wang quanyang.wang@windriver.com Signed-off-by: Michal Simek michal.simek@amd.com Link: https://lore.kernel.org/r/7e308b8efe977c4912079b4d1b1ab3d24908559e.175679977... Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index e11d282462bd3..23d867c03263d 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -550,6 +550,7 @@ reg = <0x0 0xfec10000 0x0 0x1000>; clock-names = "apb_pclk"; cpu = <&cpu0>; + status = "disabled"; };
cpu1_debug: debug@fed10000 { @@ -557,6 +558,7 @@ reg = <0x0 0xfed10000 0x0 0x1000>; clock-names = "apb_pclk"; cpu = <&cpu1>; + status = "disabled"; };
cpu2_debug: debug@fee10000 { @@ -564,6 +566,7 @@ reg = <0x0 0xfee10000 0x0 0x1000>; clock-names = "apb_pclk"; cpu = <&cpu2>; + status = "disabled"; };
cpu3_debug: debug@fef10000 { @@ -571,6 +574,7 @@ reg = <0x0 0xfef10000 0x0 0x1000>; clock-names = "apb_pclk"; cpu = <&cpu3>; + status = "disabled"; };
/* GDMA */