Hi Shimoda-san,
On Wed, Oct 9, 2019 at 6:03 AM Yoshihiro Shimoda yoshihiro.shimoda.uh@renesas.com wrote:
According to the R-Car Gen2/3 manual, the bit 0 of MACCTLR register should be written to 0 because the register is set to 1 on reset. To avoid unexpected behaviors from this incorrect setting, this patch fixes it.
Fixes: b3327f7fae66 ("PCI: rcar: Try increasing PCIe link speed to 5 GT/s at boot") Cc: stable@vger.kernel.org # v4.9+ Signed-off-by: Yoshihiro Shimoda yoshihiro.shimoda.uh@renesas.com Reviewed-by: Sergei Shtylyov sergei.shtylyov@cogentembedded.com
Thanks for your patch!
This patch fixes the issue where the register is written, so Reviewed-by: Geert Uytterhoeven geert+renesas@glider.be
However, according to the R-Car H1, Gen2, and Gen3 Hardware User's Manuals, this reserved bit should be cleared on initialization. Are we sure that is guaranteed to happen? If the checks at the top of rcar_pcie_force_speedup() trigger, the register is never written to, and the bit may still be set?
Gr{oetje,eeting}s,
Geert