From: Jun Lei Jun.Lei@amd.com
[ Upstream commit 8775e89fa7121535d2da738c95167b8c65aa6e90 ]
[why] A display that supports DRR can never really be considered "synchronized" with any other display because we can dynamically enable DRR (i.e. without modeset). this will cause their relative CRTC positions to drift and lose sync. this will disrupt features such as MCLK switching that assume and depend on their permanent alignment (that can only change with modeset)
[how] check for ignore_msa in stream when considered synchronizability this ignore_msa is basically actually implemented as "supports drr"
Signed-off-by: Jun Lei Jun.Lei@amd.com Reviewed-by: Yongqiang Sun yongqiang.sun@amd.com Acked-by: Anthony Koo Anthony.Koo@amd.com Acked-by: Leo Li sunpeng.li@amd.com Signed-off-by: Alex Deucher alexander.deucher@amd.com Signed-off-by: Sasha Levin sashal@kernel.org --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 68db60e4caf32..d1a33e04570f4 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -394,6 +394,9 @@ bool resource_are_streams_timing_synchronizable( if (stream1->view_format != stream2->view_format) return false;
+ if (stream1->ignore_msa_timing_param || stream2->ignore_msa_timing_param) + return false; + return true; } static bool is_dp_and_hdmi_sharable( @@ -1566,6 +1569,9 @@ bool dc_is_stream_unchanged( if (!are_stream_backends_same(old_stream, stream)) return false;
+ if (old_stream->ignore_msa_timing_param != stream->ignore_msa_timing_param) + return false; + return true; }