On 12/12/2022 6:03 PM, Manivannan Sadhasivam wrote:
The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size.
Also, let's get rid of reg-names property as it is not needed anymore. The driver is expected to parse the reg field based on index to get the addresses of each LLCC banks.
Cc: stable@vger.kernel.org # 5.18 Fixes: 1dc3e50eb680 ("arm64: dts: qcom: sm8450: Add LLCC/system-cache-controller node") Reported-by: Parikshit Pareek quic_ppareek@quicinc.com Signed-off-by: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
arch/arm64/boot/dts/qcom/sm8450.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 570475040d95..30685857021a 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3640,8 +3640,9 @@ gem_noc: interconnect@19100000 { system-cache-controller@19200000 { compatible = "qcom,sm8450-llcc";
reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>;reg-names = "llcc_base", "llcc_broadcast_base";
reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>,<0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>,<0 0x19a00000 0 0x80000>; interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
Reviewed-by: Sai Prakash Ranjan quic_saipraka@quicinc.com