8 Jun
2020
8 Jun
'20
11:16 a.m.
On Sun, Jun 07, 2020 at 10:09:11PM +0200, Pavel Machek wrote:
Because of out-of-order execution about some CPU architecture, In this debug stage we find Completing spi interrupt enable -> prodrucing TXEI interrupt -> running "interrupt_transfer" function will prior to set "dw->rx and dws->rx_end" data, so this patch add memory barrier to enable dw->rx and dw->rx_end to be visible and solve to send SPI data error.
So, this is apparently CPU-vs-device issue...
The commit message is a bit unclear but my read had been interrupt handler racing with sending new data rather than an ordering issue with writes to the hardware.