From: Shubhrajyoti Datta shubhrajyoti.datta@amd.com
[ Upstream commit 7c2e86f7b5af93d0e78c16e4359318fe7797671d ]
The output clock register offset used in clk_wzrd_register_output_clocks was incorrectly referencing 0x3C instead of 0x38, which caused misconfiguration of output dividers on Versal platforms.
Correcting the off-by-one error ensures proper configuration of output clocks.
Signed-off-by: Shubhrajyoti Datta shubhrajyoti.datta@amd.com Signed-off-by: Stephen Boyd sboyd@kernel.org Signed-off-by: Sasha Levin sashal@kernel.org ---
LLM Generated explanations, may be completely bogus:
YES – the change in `drivers/clk/xilinx/clk-xlnx-clock-wizard.c:1120` moves the Versal per-output divider base from `WZRD_CLK_CFG_REG(is_versal, 3)` to `... 2`, fixing the off-by-one that pointed each divider at the wrong MMIO pair.
- With the old offset, `clk_wzrd_ver_register_divider()` handed `clk_wzrd_ver_dynamic_reconfig()` a base that skips the first 32-bit register. You can see in `clk_wzrd_ver_dynamic_reconfig()` (`drivers/clk/xilinx/clk-xlnx-clock-wizard.c:235-262`) that we expect `div_addr` to hold the low/high-time bits (`WZRD_CLKFBOUT_PREDIV2`, `WZRD_EDGE_SHIFT`, etc.) and we write the high-time value to `div_addr + 4`. Starting from `... + 3` caused us to read/write the wrong register pair—programming the high-time word first and then trampling the next output’s low-time register—so the dividers for every Versal output were misconfigured. - The corrected offset now matches the register map already hard-coded elsewhere (e.g., the `DIV_ALL` path in `clk_wzrd_dynamic_ver_all_nolock()` uses `WZRD_CLK_CFG_REG(1, WZRD_CLKOUT0_1)` where `WZRD_CLKOUT0_1` is 2). That consistency makes the fix obviously right and keeps the non-Versal path untouched because the change sits under `if (is_versal)`. - The regression was introduced with Versal support (`Fixes: 3a96393a46e78`, first in v6.10), so every stable branch carrying that commit currently ships broken output clocks; the patch is a tiny, self-contained offset adjustment and does not depend on newer infrastructure, making it straightforward to backport.
Given the severity (Versal outputs can’t be programmed correctly) and the minimal, well-scoped fix, this is a strong stable-candidate. Suggested follow-up: once backported, validate on a Versal board to confirm the dividers now lock to requested rates.
drivers/clk/xilinx/clk-xlnx-clock-wizard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c index 0295a13a811cf..f209a02e82725 100644 --- a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c +++ b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c @@ -1108,7 +1108,7 @@ static int clk_wzrd_register_output_clocks(struct device *dev, int nr_outputs) (dev, clkout_name, clk_name, 0, clk_wzrd->base, - (WZRD_CLK_CFG_REG(is_versal, 3) + i * 8), + (WZRD_CLK_CFG_REG(is_versal, 2) + i * 8), WZRD_CLKOUT_DIVIDE_SHIFT, WZRD_CLKOUT_DIVIDE_WIDTH, CLK_DIVIDER_ONE_BASED |