27 Jun
2021
27 Jun
'21
11:41 p.m.
Quoting Dinh Nguyen (2021-06-10 19:52:00)
The EMAC clocks on Stratix10/Agilex/N5X have an additional bypass that was not being accounted for. The bypass selects between emaca_clk/emacb_clk and boot_clk.
Because the bypass register offset is different between Stratix10 and Agilex/N5X, it's best to create a new function to calculate the bypass.
Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform") Cc: stable@vger.kernel.org Signed-off-by: Dinh Nguyen dinguyen@kernel.org
Applied to clk-next