The patch below does not apply to the 6.10-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to stable@vger.kernel.org.
To reproduce the conflict and resubmit, you may use the following commands:
git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.10.y git checkout FETCH_HEAD git cherry-pick -x 58acedd7849a238d2d06430b030b365cf069cca8 # <resolve conflicts, build, test, etc.> git commit -s git send-email --to 'stable@vger.kernel.org' --in-reply-to '2024081224-wilder-conductor-2daa@gregkh' --subject-prefix 'PATCH 6.10.y' HEAD^..
Possible dependencies:
58acedd7849a ("drm/amd/display: Fix 1DLUT setting for NL SDR blending") 70839da63605 ("drm/amd/display: Add new DCN401 sources")
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From 58acedd7849a238d2d06430b030b365cf069cca8 Mon Sep 17 00:00:00 2001 From: Relja Vojvodic relja.vojvodic@amd.com Date: Fri, 14 Jun 2024 16:49:44 -0400 Subject: [PATCH] drm/amd/display: Fix 1DLUT setting for NL SDR blending
[WHY] Enabling NL SDR blending caused the 1D LUTs to be set/populated in two different functions. This caused flickering as the LUT was set differently by the two functions, one of which should only have been modifying the 1D LUT if 3D LUT was enabled.
[HOW] Added check to only modify the 1D LUT in populate_mcm if 3D LUT was enabled.
Added blend_tf function update for non-main planes if the 3D LUT path was taken.
Reviewed-by: Ilya Bakoulin ilya.bakoulin@amd.co Cc: Mario Limonciello mario.limonciello@amd.com Cc: Alex Deucher alexander.deucher@amd.com Cc: stable@vger.kernel.org Signed-off-by: Alex Hung alex.hung@amd.com Signed-off-by: Relja Vojvodic relja.vojvodic@amd.com Tested-by: Daniel Wheeler daniel.wheeler@amd.com Signed-off-by: Alex Deucher alexander.deucher@amd.com
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 5306c8c170c5..b5a02a8fc9d8 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -502,7 +502,7 @@ void dcn401_populate_mcm_luts(struct dc *dc, dcn401_get_mcm_lut_xable_from_pipe_ctx(dc, pipe_ctx, &shaper_xable, &lut3d_xable, &lut1d_xable);
/* 1D LUT */ - if (mcm_luts.lut1d_func) { + if (mcm_luts.lut1d_func && lut3d_xable != MCM_LUT_DISABLE) { memset(&m_lut_params, 0, sizeof(m_lut_params)); if (mcm_luts.lut1d_func->type == TF_TYPE_HWPWL) m_lut_params.pwl = &mcm_luts.lut1d_func->pwl; @@ -674,7 +674,7 @@ bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx, mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id); pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE; // 1D LUT - if (!plane_state->mcm_lut1d_enable) { + if (plane_state->mcm_shaper_3dlut_setting == DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL) { if (plane_state->blend_tf.type == TF_TYPE_HWPWL) lut_params = &plane_state->blend_tf.pwl; else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) {