These chips must be described as none of the block protection information are discoverable. This chip supports 4 bits plus the top/bottom addressing capability to identify the protected blocks.
Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal miquel.raynal@bootlin.com --- $ cat /sys/bus/spi/devices/spi0.0/spi-nor/partname cat: can't open '/sys/bus/spi/devices/spi0.0/spi-nor/partname': No such file or directory $ cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id ef8022 $ cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer winbond $ xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp 53464450060101ff00060110800000ff84000102d00000ff03000102f000 00ffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffe520fbffffffff7f44eb086b083b42bbfeffffffffff 0000ffff40eb0c200f5210d800003652b50082ea14e2e96376337a757a75 f7a2d55c199148ffe970f8a1ffffffffffffffffffffffffffffffffff0a f0ff21ffdcff $ sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp 679145368f2188ac975ec3f4c9b691e7e250147c13b6f18a28a9192700925d95 /sys/bus/spi/devices/spi0.0/spi-nor/sfdp $ cat /sys/kernel/debug/spi-nor/spi0.0/params name (null) id ef 80 22 00 00 00 size 256 MiB write size 1 page size 256 address nbytes 4 flags HAS_SR_TB | 4B_OPCODES | HAS_4BAIT | HAS_LOCK | HAS_16BIT_SR | NO_READ_CR | HAS_SR_TB_BIT6 | HAS_4BIT_BP | SOFT_RESET | NO_WP
opcodes read 0xec dummy cycles 6 erase 0xdc program 0x34 8D extension none
protocols read 1S-4S-4S write 1S-1S-4S register 1S-1S-1S
erase commands 21 (4.00 KiB) [1] dc (64.0 KiB) [3] c7 (256 MiB)
sector map region (in hex) | erase mask | overlaid ------------------+------------+--------- 00000000-0fffffff | [ 3] | no $ cat /sys/kernel/debug/spi-nor/spi0.0/capabilities Supported read modes by the flash 1S-1S-1S opcode 0x13 mode cycles 0 dummy cycles 0 1S-1S-2S opcode 0x3c mode cycles 0 dummy cycles 8 1S-2S-2S opcode 0xbc mode cycles 2 dummy cycles 2 1S-1S-4S opcode 0x6c mode cycles 0 dummy cycles 8 1S-4S-4S opcode 0xec mode cycles 2 dummy cycles 4 4S-4S-4S opcode 0xec mode cycles 2 dummy cycles 0
Supported page program modes by the flash 1S-1S-1S opcode 0x12 1S-1S-4S opcode 0x34 $ dd if=/dev/urandom of=./spi_test bs=1M count=2 2+0 records in 2+0 records out $ mtd_debug erase /dev/mtd0 0 2097152 Erased 2097152 bytes from address 0x00000000 in flash $ mtd_debug read /dev/mtd0 0 2097152 spi_read Copied 2097152 bytes from address 0x00000000 in flash to spi_read $ hexdump spi_read 0000000 ffff ffff ffff ffff ffff ffff ffff ffff * 0200000 $ sha256sum spi_read 4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read $ mtd_debug write /dev/mtd0 0 2097152 spi_test Copied 2097152 bytes from spi_test to address 0x00000000 in flash $ mtd_debug read /dev/mtd0 0 2097152 spi_read Copied 2097152 bytes from address 0x00000000 in flash to spi_read $ sha256sum spi* 5cff8d15609f3eab8d8008699191d5418da5b346e4f98ab67d5d89702b584042 spi_read 5cff8d15609f3eab8d8008699191d5418da5b346e4f98ab67d5d89702b584042 spi_test $ mtd_debug erase /dev/mtd0 0 2097152 Erased 2097152 bytes from address 0x00000000 in flash $ mtd_debug read /dev/mtd0 0 2097152 spi_read Copied 2097152 bytes from address 0x00000000 in flash to spi_read $ sha256sum spi* 4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read 5cff8d15609f3eab8d8008699191d5418da5b346e4f98ab67d5d89702b584042 spi_test $ mtd_debug info /dev/mtd0 mtd.type = MTD_NORFLASH mtd.flags = MTD_CAP_NORFLASH mtd.size = 268435456 (256M) mtd.erasesize = 65536 (64K) mtd.writesize = 1 mtd.oobsize = 0 regions = 0 --- drivers/mtd/spi-nor/winbond.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index 580c9cb37958136e7e9fbc71152de55ab008812e..a65cbbccbbac64c83227c8158ff85abfa3441868 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -351,6 +351,10 @@ static const struct flash_info winbond_nor_parts[] = { /* W25Q01NWxxIM */ .id = SNOR_ID(0xef, 0x80, 0x21), .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP, + }, { + /* W25Q02NWxxIM */ + .id = SNOR_ID(0xef, 0x80, 0x22), + .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP, }, };