6.5-stable review patch. If anyone has any objections, please let me know.
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From: Ilkka Koskinen ilkka@os.amperecomputing.com
[ Upstream commit b8af10062df3c23fe002c3f187389bb263b3eb20 ]
amperene/cache.json file tried to include L1D_CACHE_LMISS while it doesn't exist in common-and-microarch.json. While this bug doesn't seem to cause issue in newer kernels with jevents.py script, it prevents building older perf tools with the backported patch.
Fixes: a9650b7f6fc09d16 ("perf vendor events arm64: Add AmpereOne core PMU events") Reported-by: Dave Kleikamp dave.kleikamp@oracle.com Reviewed-by: Ian Rogers irogers@google.com Reviewed-by: John Garry john.g.garry@oracle.com Signed-off-by: Ilkka Koskinen ilkka@os.amperecomputing.com Cc: Adrian Hunter adrian.hunter@intel.com Cc: Alexander Shishkin alexander.shishkin@linux.intel.com Cc: Ilkka Koskinen ilkka@os.amperecomputing.com Cc: Ingo Molnar mingo@redhat.com Cc: James Clark james.clark@arm.com Cc: Jiri Olsa jolsa@kernel.org Cc: Leo Yan leo.yan@linaro.org Cc: Mark Rutland mark.rutland@arm.com Cc: Mike Leach mike.leach@linaro.org Cc: Namhyung Kim namhyung@kernel.org Cc: Peter Zijlstra peterz@infradead.org Cc: Will Deacon will@kernel.org Cc: linux-arm-kernel@lists.infradead.org Closes: https://lore.kernel.org/all/76bb2e47-ce44-76ae-838e-53279047084d@oracle.com/ Link: https://lore.kernel.org/r/20230803211331.140553-2-ilkka@os.amperecomputing.c... Signed-off-by: Arnaldo Carvalho de Melo acme@redhat.com Signed-off-by: Sasha Levin sashal@kernel.org --- tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json | 3 --- 1 file changed, 3 deletions(-)
diff --git a/tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json b/tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json index fc06330542116..7a2b7b200f144 100644 --- a/tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json +++ b/tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json @@ -92,9 +92,6 @@ { "ArchStdEvent": "L1D_CACHE_LMISS_RD" }, - { - "ArchStdEvent": "L1D_CACHE_LMISS" - }, { "ArchStdEvent": "L1I_CACHE_LMISS" },