On Tue, 12 Nov 2024 02:36:54 +0100, Marek Vasut wrote:
The CLKOUTn may be fed from PLL1/2/3, but the PLL1/2/3 has to be enabled first by setting PLL_CLKE bit 11 in CCM_ANALOG_SYS_PLLn_GEN_CTRL register. The CCM_ANALOG_SYS_PLLn_GEN_CTRL bit 11 is modeled by plln_out clock. Fix the clock tree and place the clkout1/2 under plln_sel instead of plain plln to let the clock subsystem correctly control the bit 11 and enable the PLL in case the CLKOUTn is supplied by PLL1/2/3.
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Applied, thanks!
[1/1] clk: imx8mp: Fix clkout1/2 support commit: a9b7c84d22fb1687d63ca2a386773015cf59436b
Best regards,