On Sun, Nov 02, 2025 at 11:19:02PM +0900, gregkh@linuxfoundation.org wrote:
+static const struct x86_cpu_id zen5_rdseed_microcode[] = {
- ZEN_MODEL_STEP_UCODE(0x1a, 0x02, 0x1, 0x0b00215a),
- ZEN_MODEL_STEP_UCODE(0x1a, 0x11, 0x0, 0x0b101054),
+};
Yeah, we don't have that min microcode gunk with the device_id match so we'll have to do something like we did for TSA. I.e., below.
I'll test it tomorrow to make sure it doesn't do any cat incinerations :-P
---
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 18518a481016..437c1db652e9 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -1018,14 +1018,39 @@ static void init_amd_zen4(struct cpuinfo_x86 *c) } }
-static const struct x86_cpu_id zen5_rdseed_microcode[] = { - ZEN_MODEL_STEP_UCODE(0x1a, 0x02, 0x1, 0x0b00215a), - ZEN_MODEL_STEP_UCODE(0x1a, 0x11, 0x0, 0x0b101054), -}; +static bool check_rdseed_microcode(void) +{ + struct cpuinfo_x86 *c = &boot_cpu_data; + union zen_patch_rev p; + u32 min_rev = 0; + + p.ext_fam = c->x86 - 0xf; + p.model = c->x86_model; + p.ext_model = c->x86_model >> 4; + p.stepping = c->x86_stepping; + /* reserved bits are expected to be 0 in test below */ + p.__reserved = 0; + + if (cpu_has(c, X86_FEATURE_ZEN5)) { + switch (p.ucode_rev >> 8) { + case 0xb0021: min_rev = 0xb00215a; break; + case 0xb1010: min_rev = 0xb101054; break; + default: + pr_debug("%s: ucode_rev: 0x%x, current revision: 0x%x\n", + __func__, p.ucode_rev, c->microcode); + return false; + } + } + + if (!min_rev) + return false; + + return c->microcode >= min_rev; +}
static void init_amd_zen5(struct cpuinfo_x86 *c) { - if (!x86_match_min_microcode_rev(zen5_rdseed_microcode)) { + if (!check_rdseed_microcode()) { clear_cpu_cap(c, X86_FEATURE_RDSEED); msr_clear_bit(MSR_AMD64_CPUID_FN_7, 18); pr_emerg_once("RDSEED32 is broken. Disabling the corresponding CPUID bit.\n");