From: Otavio Salvador otavio@ossystems.com.br
[ Upstream commit efc2e0bd9594060915696a418564aefd0270b1d6 ]
It is not correct to assign the 24MHz clock oscillator to the GPIO ports.
Fix it by assigning the proper GPIO clocks instead.
Signed-off-by: Otavio Salvador otavio@ossystems.com.br Tested-by: Fabio Berton fabio.berton@ossystems.com.br Signed-off-by: Heiko Stuebner heiko@sntech.de Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm/boot/dts/rv1108.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index 4090ad2619ffb..a9f053dfdc068 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -541,7 +541,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x20030000 0x100>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&xin24m>; + clocks = <&cru PCLK_GPIO0_PMU>;
gpio-controller; #gpio-cells = <2>; @@ -554,7 +554,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x10310000 0x100>; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&xin24m>; + clocks = <&cru PCLK_GPIO1>;
gpio-controller; #gpio-cells = <2>; @@ -567,7 +567,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x10320000 0x100>; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&xin24m>; + clocks = <&cru PCLK_GPIO2>;
gpio-controller; #gpio-cells = <2>; @@ -580,7 +580,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x10330000 0x100>; interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&xin24m>; + clocks = <&cru PCLK_GPIO3>;
gpio-controller; #gpio-cells = <2>;