From: Jonathan Cameron Jonathan.Cameron@huawei.com
[ Upstream commit 37882314d3bdc2ae775ebb9fa8ed7a94cd1aad61 ]
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition.
Fixes tag is probably not where the issue was first introduced, but is likely to be as far as anyone considers backporting this fix.
Fixes: 0bd3d338f61b ("staging: iio: ad2s1200: Improve readability with be16_to_cpup") Signed-off-by: Jonathan Cameron Jonathan.Cameron@huawei.com Acked-by: Nuno Sá nuno.sa@analog.com Link: https://lore.kernel.org/r/20220508175712.647246-89-jic23@kernel.org Signed-off-by: Sasha Levin sashal@kernel.org --- drivers/iio/resolver/ad2s1200.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iio/resolver/ad2s1200.c b/drivers/iio/resolver/ad2s1200.c index 9746bd935628..9d95241bdf8f 100644 --- a/drivers/iio/resolver/ad2s1200.c +++ b/drivers/iio/resolver/ad2s1200.c @@ -41,7 +41,7 @@ struct ad2s1200_state { struct spi_device *sdev; struct gpio_desc *sample; struct gpio_desc *rdvel; - __be16 rx ____cacheline_aligned; + __be16 rx __aligned(IIO_DMA_MINALIGN); };
static int ad2s1200_read_raw(struct iio_dev *indio_dev,