From: Taniya Das quic_tdas@quicinc.com
[ Upstream commit 201bf08ba9e26eeb0a96ba3fd5c026f531b31aed ]
Update the force mem core bit for UFS ICE clock and UFS PHY AXI clock to force the core on signal to remain active during halt state of the clk. If force mem core bit of the clock is not set, the memories of the subsystem will not retain the logic across power states. This is required for the MCQ feature of UFS.
Signed-off-by: Taniya Das quic_tdas@quicinc.com Reviewed-by: Imran Shaik quic_imrashai@quicinc.com Link: https://lore.kernel.org/r/20250414-gcc_ufs_mem_core-v1-2-67b5529b9b5d@quicin... Signed-off-by: Bjorn Andersson andersson@kernel.org Signed-off-by: Sasha Levin sashal@kernel.org ---
**YES** This commit should be backported to stable kernel trees. Here's my extensive analysis: ## Key Factors Supporting Backporting: ### 1. **Bug Fix Nature with Clear Functional Impact** The commit fixes a real functional bug where UFS memories fail to retain logic across power states when the FORCE_MEM_CORE_ON bit is not set. This directly impacts the MCQ (Multi Circular Queue) feature of UFS, which is a performance- critical functionality for storage operations. ### 2. **Minimal and Contained Code Changes** The actual code change is extremely small and surgical: ```c + /bin /bin.usr-is-merged /boot /dev /etc /home /init /lib /lib.usr-is-merged /lib64 /lost+found /media /mnt /opt /proc /root /run /sbin /sbin.usr-is-merged /snap /srv /sys /tmp /usr /var FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks linux/ + qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); + qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true); ``` This is just two function calls that set specific register bits (BIT(14) in the halt registers) to ensure memory retention during clock halt states. ### 3. **Strong Pattern Match with Accepted Backports** Looking at the historical examples: - **Similar Commit #2 (YES)**: Nearly identical fix for SC7280 platform setting FORCE_MEM_CORE_ON for UFS ICE clock - **Similar Commit #5 (YES)**: UFS clock fixes for MSM8998 that improve UFS functionality The pattern is clear: UFS clock fixes that address hardware requirements are consistently backported. ### 4. **Low Regression Risk** - The change only affects two specific UFS clocks on the x1e80100 platform - Uses an existing, well-tested function (`qcom_branch_set_force_mem_core`) - Only sets bits to ensure memory retention - cannot break existing functionality - Platform-specific change that won't affect other hardware ### 5. **Critical for Hardware Functionality** The commit message explicitly states this is "required for the MCQ feature of UFS." MCQ is not an optional enhancement but a fundamental part of modern UFS operation for performance and reliability. ### 6. **Follows Established Qualcomm Pattern** My kernel tree analysis shows this exact pattern implemented across multiple Qualcomm platforms (SM8650, SM8750, SA8775P, SC7280), indicating this is a well-understood hardware requirement rather than an experimental change. ### 7. **Platform-Specific Scope** The change is confined to `drivers/clk/qcom/gcc-x1e80100.c`, affecting only the Qualcomm X1E80100 platform. This isolation minimizes any risk to other systems. ## Code Analysis Details: The fix sets `CBCR_FORCE_MEM_CORE_ON` (BIT(14)) in the halt registers of: - `gcc_ufs_phy_ice_core_clk` (halt_reg = 0x77074) - `gcc_ufs_phy_axi_clk` (halt_reg = 0x77018) This ensures that when these clocks enter halt state, the core memory remains powered and retains its state, which is essential for the UFS MCQ feature to function correctly across power transitions. The change aligns perfectly with stable kernel criteria: it's a small, contained bug fix that addresses a real hardware requirement with minimal regression risk.
drivers/clk/qcom/gcc-x1e80100.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/clk/qcom/gcc-x1e80100.c b/drivers/clk/qcom/gcc-x1e80100.c index 009f39139b644..3e44757e25d32 100644 --- a/drivers/clk/qcom/gcc-x1e80100.c +++ b/drivers/clk/qcom/gcc-x1e80100.c @@ -6753,6 +6753,10 @@ static int gcc_x1e80100_probe(struct platform_device *pdev) /* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */ regmap_write(regmap, 0x52224, 0x0);
+ /* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks */ + qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); + qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true); + return qcom_cc_really_probe(&pdev->dev, &gcc_x1e80100_desc, regmap); }