6.1-stable review patch. If anyone has any objections, please let me know.
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From: Maher Sanalla msanalla@nvidia.com
[ Upstream commit 8d231dbc3b10155727bcfa9e543d397ad357f14f ]
Add the shared receive buffer management and configuration registers: 1. SBPR - Shared Buffer Pools Register 2. SBCM - Shared Buffer Class Management Register
Signed-off-by: Maher Sanalla msanalla@nvidia.com Reviewed-by: Moshe Shemesh moshe@nvidia.com Signed-off-by: Saeed Mahameed saeedm@nvidia.com Stable-dep-of: 9fcc2b6c1052 ("net/mlx5e: Fix potentially misleading debug message") Signed-off-by: Sasha Levin sashal@kernel.org --- include/linux/mlx5/driver.h | 2 ++ include/linux/mlx5/mlx5_ifc.h | 61 +++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+)
diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index b05f69a8306c9..9af7180eac9e3 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -100,6 +100,8 @@ enum { };
enum { + MLX5_REG_SBPR = 0xb001, + MLX5_REG_SBCM = 0xb002, MLX5_REG_QPTS = 0x4002, MLX5_REG_QETCR = 0x4005, MLX5_REG_QTCT = 0x400a, diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 271c5a87751fe..4df7b3d358607 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -10930,6 +10930,67 @@ struct mlx5_ifc_pbmc_reg_bits { u8 reserved_at_2e0[0x80]; };
+struct mlx5_ifc_sbpr_reg_bits { + u8 desc[0x1]; + u8 snap[0x1]; + u8 reserved_at_2[0x4]; + u8 dir[0x2]; + u8 reserved_at_8[0x14]; + u8 pool[0x4]; + + u8 infi_size[0x1]; + u8 reserved_at_21[0x7]; + u8 size[0x18]; + + u8 reserved_at_40[0x1c]; + u8 mode[0x4]; + + u8 reserved_at_60[0x8]; + u8 buff_occupancy[0x18]; + + u8 clr[0x1]; + u8 reserved_at_81[0x7]; + u8 max_buff_occupancy[0x18]; + + u8 reserved_at_a0[0x8]; + u8 ext_buff_occupancy[0x18]; +}; + +struct mlx5_ifc_sbcm_reg_bits { + u8 desc[0x1]; + u8 snap[0x1]; + u8 reserved_at_2[0x6]; + u8 local_port[0x8]; + u8 pnat[0x2]; + u8 pg_buff[0x6]; + u8 reserved_at_18[0x6]; + u8 dir[0x2]; + + u8 reserved_at_20[0x1f]; + u8 exc[0x1]; + + u8 reserved_at_40[0x40]; + + u8 reserved_at_80[0x8]; + u8 buff_occupancy[0x18]; + + u8 clr[0x1]; + u8 reserved_at_a1[0x7]; + u8 max_buff_occupancy[0x18]; + + u8 reserved_at_c0[0x8]; + u8 min_buff[0x18]; + + u8 infi_max[0x1]; + u8 reserved_at_e1[0x7]; + u8 max_buff[0x18]; + + u8 reserved_at_100[0x20]; + + u8 reserved_at_120[0x1c]; + u8 pool[0x4]; +}; + struct mlx5_ifc_qtct_reg_bits { u8 reserved_at_0[0x8]; u8 port_number[0x8];