From: Marijn Suijten marijn.suijten@somainline.org
[ Upstream commit cbfb5668aece448877fa7826cde81c9d06f4a4ac ]
According to qcom,sm6125-pinctrl.yaml all nodes inside the tlmm must be suffixed by -state:
qcom/sm6125-sony-xperia-seine-pdx201.dtb: pinctrl@500000: 'sdc2-off', 'sdc2-on' do not match any of the regexes: '-state$', 'pinctrl-[0-9]+'
The label names have been updated to match, going from sdc2_state_X to sdc2_X_state.
Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125") Fixes: 82e1783890b7 ("arm64: dts: qcom: sm6125: Add support for Sony Xperia 10II") Signed-off-by: Marijn Suijten marijn.suijten@somainline.org Signed-off-by: Bjorn Andersson bjorn.andersson@linaro.org Link: https://lore.kernel.org/r/20220508100336.127176-2-marijn.suijten@somainline.... Signed-off-by: Sasha Levin sashal@kernel.org --- .../boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm6125.dtsi | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts index 4916e6c8b625..038970c0b68e 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts @@ -88,7 +88,7 @@ &hsusb_phy1 { status = "okay"; };
-&sdc2_state_off { +&sdc2_off_state { sd-cd { pins = "gpio98"; drive-strength = <2>; @@ -96,7 +96,7 @@ sd-cd { }; };
-&sdc2_state_on { +&sdc2_on_state { sd-cd { pins = "gpio98"; drive-strength = <2>; diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index a0d8580739c5..5ee1e4b20301 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -386,7 +386,7 @@ tlmm: pinctrl@500000 { interrupt-controller; #interrupt-cells = <2>;
- sdc2_state_off: sdc2-off { + sdc2_off_state: sdc2-off-state { clk { pins = "sdc2_clk"; drive-strength = <2>; @@ -406,7 +406,7 @@ data { }; };
- sdc2_state_on: sdc2-on { + sdc2_on_state: sdc2-on-state { clk { pins = "sdc2_clk"; drive-strength = <16>; @@ -490,8 +490,8 @@ sdhc_2: sdhci@4784000 { <&xo_board>; clock-names = "iface", "core", "xo";
- pinctrl-0 = <&sdc2_state_on>; - pinctrl-1 = <&sdc2_state_off>; + pinctrl-0 = <&sdc2_on_state>; + pinctrl-1 = <&sdc2_off_state>; pinctrl-names = "default", "sleep";
power-domains = <&rpmpd SM6125_VDDCX>;