From: Nicholas Kazlauskas nicholas.kazlauskas@amd.com
commit 672437486ee9da3ed0e774937e6d0dd570921b39 upstream.
[Why] Immediate flip can be enabled dynamically and has higher BW requirements when validating which voltage mode to use.
If we validate when it's not set then potentially DCFCLK will be too low and we will underflow.
[How] DM always requires support so always require it as part of DML input parameters.
This can't be enabled unconditionally on older ASIC because it blocks some expected modes so only target DCN3.1 for now.
Reviewed-by: Dmytro Laktyushkin Dmytro.Laktyushkin@amd.com Acked-by: Agustin Gutierrez Sanchez agustin.gutierrez@amd.com Signed-off-by: Nicholas Kazlauskas nicholas.kazlauskas@amd.com Tested-by: Daniel Wheeler daniel.wheeler@amd.com Signed-off-by: Alex Deucher alexander.deucher@amd.com Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman gregkh@linuxfoundation.org --- drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 7 +++++++ 1 file changed, 7 insertions(+)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c @@ -1591,6 +1591,13 @@ static int dcn31_populate_dml_pipes_from pipe = &res_ctx->pipe_ctx[i]; timing = &pipe->stream->timing;
+ /* + * Immediate flip can be set dynamically after enabling the plane. + * We need to require support for immediate flip or underflow can be + * intermittently experienced depending on peak b/w requirements. + */ + pipes[pipe_cnt].pipe.src.immediate_flip = true; + pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; pipes[pipe_cnt].pipe.src.gpuvm = true; pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;