On Mon, Dec 31, 2018 at 11:14:28AM +0100, Krzysztof Hałasa wrote:
Bjorn Helgaas helgaas@kernel.org writes:
802b7c06adc7 replaced cns3xxx_pci_write_config(), which always used __raw_writel() so it only did 32-bit accesses, with pci_generic_config_write(), which uses writeb/writew/writel() depending on the size.
802b7c06adc7 also converted cns3xxx_pci_read_config() from always using __raw_readl() (a 32-bit access) to using pci_generic_config_read32(), which also always does a 32-bit access.
This makes me think the cnx3xxx hardware is only capable of 32-bit accesses, and this patch should change the driver to use pci_generic_config_write32() instead of pci_generic_config_write() in addition to the mapping fix above.
Hasn't it already been verified that the CNS3xxx can do 8-bit accesses (and probably 16-bit ones as well), and that the docs don't mention any such limitation?
Quite possibly. I'm not familiar with the hardware or docs so can't comment personally.
802b7c06adc7 reimplemented cns3xxx_pci_read_config() using pci_generic_config_read32(), which preserved the property of only doing 32-bit reads. It replaced cns3xxx_pci_write_config() with pci_generic_config_write(), so it changed writes from always being 32 bits to being the actual size. I think this was an error in the original commit, since the changelog doesn't mention this change; in fact, the changelog says it changes __raw_writel to writel.
The change from 32-bit to actual size accesses would logically be a separate commit from changing to use the generic accessors.
Assuming the hardware does support smaller accesses, I'd propose two patches:
1) The current one that corrects the address alignment error, and 2) A new one that converts cns3xxx_pci_read_config() to use pci_generic_config_read() instead of pci_generic_config_read32().
Ideally the changelog for the second patch would refer to the verification that the hardware is capable of 8- and 16-bit accesses.
Bjorn