On Sat, Sep 11, 2021 at 06:05:37PM +0200, Marek Vasut wrote:
On 9/11/21 3:11 PM, Sasha Levin wrote:
From: Marek Vasut marek.vasut+renesas@gmail.com
[ Upstream commit a115b1bd3af0c2963e72f6e47143724c59251be6 ]
When the link is in L1, hardware should return it to L0 automatically whenever a transaction targets a component on the other end of the link (PCIe r5.0, sec 5.2).
The R-Car PCIe controller doesn't handle this transition correctly. If the link is not in L0, an MMIO transaction targeting a downstream device fails, and the controller reports an ARM imprecise external abort.
Work around this by hooking the abort handler so the driver can detect this situation and help the hardware complete the link state transition.
When the R-Car controller receives a PM_ENTER_L1 DLLP from the downstream component, it sets PMEL1RX bit in PMSR register, but then the controller enters some sort of in-between state. A subsequent MMIO transaction will fail, resulting in the external abort. The abort handler detects this condition and completes the link state transition by setting the L1IATN bit in PMCTLR and waiting for the link state transition to complete.
You will also need the following patch, otherwise the build will fail on configurations without COMMON_CLK (none where this driver is used, but happened on one of the build bots). I'm waiting for PCIe maintainers to pick it up: https://patchwork.kernel.org/project/linux-pci/patch/20210907144512.5238-1-m...
I see that it's not upstream yet, so I'll drop this patch for now.