-----Original Message----- From: Ville Syrjala ville.syrjala@linux.intel.com Sent: Thursday, October 1, 2020 4:07 AM To: intel-gfx@lists.freedesktop.org Cc: stable@vger.kernel.org; Kulkarni, Vandita vandita.kulkarni@intel.com; Shankar, Uma uma.shankar@intel.com Subject: [PATCH] drm/i915: Fix TGL DKL PHY DP vswing handling
From: Ville Syrjälä ville.syrjala@linux.intel.com
The HDMI vs. not-HDMI check got inverted whem the bogus encoder->type checks were eliminated. So now we're using 0 as the link rate on DP and potentially non-zero on HDMI, which is exactly the opposite of what we want. The original bogus check actually worked more correctly by accident since if would always evaluate to true. Due to this we now always use the RBR/HBR1 vswing table and never ever the HBR2+ vswing table. That is probably not a good way to get a high quality signal at HBR2+ rates. Fix the check so we pick the right table.
Cc: stable@vger.kernel.org Cc: Vandita Kulkarni vandita.kulkarni@intel.com Cc: Uma Shankar uma.shankar@intel.com Fixes: 94641eb6c696 ("drm/i915/display: Fix the encoder type check") Signed-off-by: Ville Syrjälä ville.syrjala@linux.intel.com
LGTM. Reviewed-by: Vandita Kulkarni vandita.kulkarni@intel.com I think I missed the inverted change while rebasing. Thanks, Vandita
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 4d06178cd76c..cdcb7b1034ae 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2742,7 +2742,7 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock, u32 n_entries, val, ln, dpcnt_mask, dpcnt_val; int rate = 0;
- if (type == INTEL_OUTPUT_HDMI) {
if (type != INTEL_OUTPUT_HDMI) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
rate = intel_dp->link_rate;
-- 2.26.2