From: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org
[ Upstream commit 42dcd054a6493e1adf292c3e246d1a2a9258942e ]
As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like:
rk3588s-khadas-edge2.dtb: l3-cache: 'cache-unified' is a dependency of 'cache-size'
Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org Link: https://lore.kernel.org/r/20230421223149.115185-1-krzysztof.kozlowski@linaro... Signed-off-by: Heiko Stuebner heiko@sntech.de Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/rockchip/rk3308.dtsi | 1 + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 1 + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 9 +++++++++ 3 files changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi index dd228a256a32a..2ae4bb7d5e62a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi @@ -97,6 +97,7 @@ CPU_SLEEP: cpu-sleep { l2: l2-cache { compatible = "cache"; cache-level = <2>; + cache-unified; }; };
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 6d7a7bf72ac7e..e729e7a22b23a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -103,6 +103,7 @@ CPU_SLEEP: cpu-sleep { l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; };
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index f4eae4dde1751..ff4470a28ffa4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -223,6 +223,7 @@ l2_cache_l0: l2-cache-l0 { cache-line-size = <64>; cache-sets = <512>; cache-level = <2>; + cache-unified; next-level-cache = <&l3_cache>; };
@@ -232,6 +233,7 @@ l2_cache_l1: l2-cache-l1 { cache-line-size = <64>; cache-sets = <512>; cache-level = <2>; + cache-unified; next-level-cache = <&l3_cache>; };
@@ -241,6 +243,7 @@ l2_cache_l2: l2-cache-l2 { cache-line-size = <64>; cache-sets = <512>; cache-level = <2>; + cache-unified; next-level-cache = <&l3_cache>; };
@@ -250,6 +253,7 @@ l2_cache_l3: l2-cache-l3 { cache-line-size = <64>; cache-sets = <512>; cache-level = <2>; + cache-unified; next-level-cache = <&l3_cache>; };
@@ -259,6 +263,7 @@ l2_cache_b0: l2-cache-b0 { cache-line-size = <64>; cache-sets = <1024>; cache-level = <2>; + cache-unified; next-level-cache = <&l3_cache>; };
@@ -268,6 +273,7 @@ l2_cache_b1: l2-cache-b1 { cache-line-size = <64>; cache-sets = <1024>; cache-level = <2>; + cache-unified; next-level-cache = <&l3_cache>; };
@@ -277,6 +283,7 @@ l2_cache_b2: l2-cache-b2 { cache-line-size = <64>; cache-sets = <1024>; cache-level = <2>; + cache-unified; next-level-cache = <&l3_cache>; };
@@ -286,6 +293,7 @@ l2_cache_b3: l2-cache-b3 { cache-line-size = <64>; cache-sets = <1024>; cache-level = <2>; + cache-unified; next-level-cache = <&l3_cache>; };
@@ -295,6 +303,7 @@ l3_cache: l3-cache { cache-line-size = <64>; cache-sets = <4096>; cache-level = <3>; + cache-unified; }; };