From: Douglas Anderson dianders@chromium.org
[ Upstream commit 37f7349b56decc91c66f8039712e63740b1f25f9 ]
There are 4 qspi data pins: data0, data1, data2, and data3. Currently we have a shared pin state for data0 and data1 (2 lane config) and a pin state for data2 and data3 (you'd enable both this and the 2 lane state for 4 lanes). The second state is obviously misnamed. Fix it.
Fixes: e1ce853932b7 ("arm64: dts: qcom: sdm845: Add qspi (quad SPI) node") Signed-off-by: Douglas Anderson dianders@chromium.org Acked-by: Linus Walleij linus.walleij@linaro.org Signed-off-by: Bjorn Andersson andersson@kernel.org Link: https://lore.kernel.org/r/20230323102605.3.I88528d037b7fda4e53a40f661be5ac61... Signed-off-by: Sasha Levin sashal@kernel.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2705,7 +2705,7 @@ }; };
- qspi_data12: qspi-data12 { + qspi_data23: qspi-data23 { pinmux-data { pins = "gpio93", "gpio94"; function = "qspi_data";