From: Jonathan Cameron Jonathan.Cameron@huawei.com
[ Upstream commit a3e38a557a54df0edea791d7eb623515bb86e39a ]
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition.
Fixes: f4eb9ac7842f ("iio: frequency: admv1014: add support for ADMV1014") Signed-off-by: Jonathan Cameron Jonathan.Cameron@huawei.com Cc: Antoniu Miclaus antoniu.miclaus@analog.com Acked-by: Nuno Sá nuno.sa@analog.com Link: https://lore.kernel.org/r/20220508175712.647246-70-jic23@kernel.org Signed-off-by: Sasha Levin sashal@kernel.org --- drivers/iio/frequency/admv1014.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iio/frequency/admv1014.c b/drivers/iio/frequency/admv1014.c index 1aac5665b5de..865addd10db4 100644 --- a/drivers/iio/frequency/admv1014.c +++ b/drivers/iio/frequency/admv1014.c @@ -127,7 +127,7 @@ struct admv1014_state { unsigned int quad_se_mode; unsigned int p1db_comp; bool det_en; - u8 data[3] ____cacheline_aligned; + u8 data[3] __aligned(IIO_DMA_MINALIGN); };
static const int mixer_vgate_table[] = {106, 107, 108, 110, 111, 112, 113, 114,