Hi,
With SRC in the firmware processing pipeline the FE and BE rate can be different, the sample counters on the two side of the DSP counts in different rate domain and they will drift apart. The counters should be moved to the same rate domain to be usable for delay calculation.
The ChainDMA offset value was incorrect since the host buffer size and the trigger to start the chain is misunderstood initially.
Finally: we can have a situation when the host and link DMA channel in HDA is not using matching channel ids. We need to look up the link channel explicitly to make sure that we read the LLP from the correct link.
Regards, Peter --- Kai Vehmanen (3): ASoC: SOF: ipc4-pcm: fix delay calculation when DSP resamples ASoC: SOF: ipc4-pcm: fix start offset calculation for chain DMA ASoC: SOF: ipc4-pcm: do not report invalid delay values
Peter Ujfalusi (2): ASoC: SOF: sof-audio: add dev_dbg_ratelimited wrapper ASoC: SOF: Intel: Read the LLP via the associated Link DMA channel
sound/soc/sof/intel/hda-stream.c | 29 ++++++++- sound/soc/sof/ipc4-pcm.c | 104 ++++++++++++++++++++++++------- sound/soc/sof/ipc4-topology.c | 1 - sound/soc/sof/ipc4-topology.h | 2 + sound/soc/sof/sof-audio.h | 5 ++ 5 files changed, 114 insertions(+), 27 deletions(-)