From: Danny Wang Danny.Wang@amd.com
[ Upstream commit ad335b5fc9ed1cdeb33fbe97d2969b3a2eedaf3e ]
[WHY&HOW] The user closed the lid while the system was powering on and opened it again before the “apply_seamless_boot_optimization” was set to false, resulting in the eDP remaining blank. Reset the “apply_seamless_boot_optimization” to false when dpms off.
Reviewed-by: Nicholas Kazlauskas nicholas.kazlauskas@amd.com Signed-off-by: Danny Wang Danny.Wang@amd.com Signed-off-by: Tom Chung chiahsuan.chung@amd.com Tested-by: Daniel Wheeler daniel.wheeler@amd.com Signed-off-by: Alex Deucher alexander.deucher@amd.com Signed-off-by: Sasha Levin sashal@kernel.org ---
LLM Generated explanations, may be completely bogus:
YES
- What it fixes: On some laptops with eDP, closing the lid during boot and reopening before the first flip leaves the panel blank. Root cause: the per‑stream flag `apply_seamless_boot_optimization` stays true if no flip occurs, so on DPMS resume the driver skips reprogramming the link and other enablement, leaving the panel dark. - Current behavior: The seamless-boot flag is only cleared after the first flip. In this tree, `update_seamless_boot_flags()` only clears it when there is a plane update: drivers/gpu/drm/amd/display/dc/core/dc.c:3393. If the only event is DPMS off, the flag remains set. - Why that blanks eDP: On DPMS on, the link enable path explicitly bails out early when `apply_seamless_boot_optimization` is true and “does not touch link,” only doing limited work for DP external displays. See drivers/gpu/drm/amd/display/dc/link/link_dpms.c:2520. For eDP, this means re-enabling doesn’t retrain/reprogram the link, so the screen can stay blank. - How the patch fixes it: The change adds `|| stream->dpms_off` to the condition in `update_seamless_boot_flags()`, so the flag is cleared not only on first flip but also when DPMS is turned off. The stream’s DPMS state is already updated earlier in the same commit path (drivers/gpu/drm/amd/display/dc/core/dc.c:3279), and the DPMS off/on programming is handled shortly after (drivers/gpu/drm/amd/display/dc/core/dc.c:3672). With the flag cleared on DPMS off, a subsequent DPMS on will no longer hit the early return in link_dpms.c, so the link gets fully reprogrammed, avoiding the blank screen. - Containment and risk: The change is a one-line conditional broadening in a helper (no API or structural changes) and only affects the seamless‑boot window. It is gated by `get_seamless_boot_stream_count(context) > 0`, so it only acts when seamless‑boot optimization is active. Clearing the optimization when the panel is already being powered down is low risk and makes the DPMS-on path behave like a normal enable rather than a seamless resume. - Interactions: This aligns with prior fixes that avoid toggling DPMS during seamless boot (e.g., “Don’t set dpms_off for seamless boot”); it closes a different corner case where DPMS is requested before the first flip. It also ensures `dc_post_update_surfaces_to_stream` isn’t indefinitely deferred by `get_seamless_boot_stream_count(context) > 0` during/after DPMS off (drivers/gpu/drm/amd/display/dc/core/dc.c:2526). - Stable backport fit: - Fixes a real user-visible bug (blank eDP after lid cycle during boot). - Minimal, self-contained change in AMDGPU DC. - No new features or architectural changes. - Uses existing fields and code paths present in stable trees. - Reviewed/acknowledged/tested in the commit message, increasing confidence.
Conclusion: This is a small, targeted bug fix with clear rationale and minimal regression risk, and should be backported to stable.
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index bc364792d9d31..2d2f4c4bdc97e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -3404,7 +3404,7 @@ static void update_seamless_boot_flags(struct dc *dc, int surface_count, struct dc_stream_state *stream) { - if (get_seamless_boot_stream_count(context) > 0 && surface_count > 0) { + if (get_seamless_boot_stream_count(context) > 0 && (surface_count > 0 || stream->dpms_off)) { /* Optimize seamless boot flag keeps clocks and watermarks high until * first flip. After first flip, optimization is required to lower * bandwidth. Important to note that it is expected UEFI will