From: Aleksander Jan Bajkowski olek2@wp.pl
[ Upstream commit e8dee66c37085dc9858eb8608bc783c2900e50e7 ]
This fixes the following warnings: arch/mips/boot/dts/lantiq/danube_easy50712.dtb: cpus: '#address-cells' is a required property from schema $id: http://devicetree.org/schemas/cpus.yaml# arch/mips/boot/dts/lantiq/danube_easy50712.dtb: cpus: '#size-cells' is a required property from schema $id: http://devicetree.org/schemas/cpus.yaml# arch/mips/boot/dts/lantiq/danube_easy50712.dtb: cpu@0 (mips,mips24Kc): 'reg' is a required property from schema $id: http://devicetree.org/schemas/mips/cpus.yaml#
Signed-off-by: Aleksander Jan Bajkowski olek2@wp.pl Signed-off-by: Thomas Bogendoerfer tsbogend@alpha.franken.de Signed-off-by: Sasha Levin sashal@kernel.org ---
LLM Generated explanations, may be completely bogus:
YES
- What it fixes - Adds required properties to the CPU description so the DT validates cleanly against schemas, eliminating build-time errors/warnings: - Adds `#address-cells = <1>` and `#size-cells = <0>` to the `cpus` node (arch/mips/boot/dts/lantiq/danube.dtsi:8–9), matching `cpus.yaml` requirements. - Adds `reg = <0>` to `cpu@0` (arch/mips/boot/dts/lantiq/danube.dtsi:13), matching `mips/cpus.yaml` requirements. - Directly addresses the warnings listed in the commit message, improving DT correctness and preventing build/CI failures in environments treating schema violations as errors.
- Scope and risk - Device Tree only; no driver or core code changes. The change is minimal and contained to a single DTSI file: `arch/mips/boot/dts/lantiq/danube.dtsi`. - The new properties are long-established, standard DT fields for CPU nodes. `reg = <0>` is the canonical single-CPU index and does not alter runtime semantics for this platform. - No architectural changes and no functional behavior changes are introduced; this is metadata correctness for DT schema compliance.
- Impact and side effects - Positive: removes DT validation warnings, improves tooling and cross-tree consistency, and avoids potential build failures in strict pipelines. - Neutral at runtime: kernel CPU enumeration for a single-core MIPS system remains unchanged; these properties are consumed by standard DT parsing code and other MIPS DTS files already follow this pattern.
- Stable backport criteria - Fixes a real (schema) bug affecting users/projects relying on DT validation, with a clear and minimal change. - No new features; no API changes; extremely low regression risk; confined to the MIPS Lantiq Danube DT.
arch/mips/boot/dts/lantiq/danube.dtsi | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/mips/boot/dts/lantiq/danube.dtsi b/arch/mips/boot/dts/lantiq/danube.dtsi index 7a7ba66aa5349..0a942bc091436 100644 --- a/arch/mips/boot/dts/lantiq/danube.dtsi +++ b/arch/mips/boot/dts/lantiq/danube.dtsi @@ -5,8 +5,12 @@ / { compatible = "lantiq,xway", "lantiq,danube";
cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { compatible = "mips,mips24Kc"; + reg = <0>; }; };