4.19-stable review patch. If anyone has any objections, please let me know.
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From: Chris Wilson chris@chris-wilson.co.uk
[ Upstream commit 79556df293b2efbb3ccebb6db02120d62e348b44 ]
We should we have all the kinks worked out and full-ppgtt now works reliably on gen7 (Ivybridge, Valleyview/Baytrail and Haswell). If we can let userspace have full control over their own ppgtt, it makes softpinning far more effective, in turn making GPU dispatch far more efficient by virtue of better mm segregation. On the other hand, switching over to a different GTT for every client does incur noticeable overhead, but only for very lightweight tasks.
Signed-off-by: Chris Wilson chris@chris-wilson.co.uk Cc: Joonas Lahtinen joonas.lahtinen@linux.intel.com Cc: Mika Kuoppala mika.kuoppala@linux.intel.com Cc: Matthew Auld matthew.william.auld@gmail.com Reviewed-by: Joonas Lahtinen joonas.lahtinen@linux.intel.com Cc: Jason Ekstrand jason.ekstrand@intel.com Cc: Kenneth Graunke kenneth@whitecape.org Acked-by: Kenneth Graunke kenneth@whitecape.org Link: https://patchwork.freedesktop.org/patch/msgid/20180717095751.1034-1-chris@ch... Stable-dep-of: ffcde9e44d3e ("drm: fsl-dcu: enable PIXCLK on LS1021A") Signed-off-by: Sasha Levin sashal@kernel.org --- drivers/gpu/drm/i915/i915_gem_gtt.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index d4c6aa7fbac8d..0b5b45fe0fe78 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -180,13 +180,11 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, return 0; }
- if (HAS_LOGICAL_RING_CONTEXTS(dev_priv)) { - if (has_full_48bit_ppgtt) - return 3; + if (has_full_48bit_ppgtt) + return 3;
- if (has_full_ppgtt) - return 2; - } + if (has_full_ppgtt) + return 2;
return 1; }