[PATCH AUTOSEL 5.15 4/5] MIPS: Loongson64: DTS: Really fix PCIe port nodes for ls7a

4 Dec 2024

From: Xi Ruoyao xry111@xry111.site
[ Upstream commit 4fbd66d8254cedfd1218393f39d83b6c07a01917 ]
Fix the dtc warnings:
arch/mips/boot/dts/loongson/ls7a-pch.dtsi:68.16-416.5: Warning (interrupt_provider): /bus@10000000/pci@1a000000: '#interrupt-cells' found, but node is not an interrupt provider
    arch/mips/boot/dts/loongson/ls7a-pch.dtsi:68.16-416.5: Warning (interrupt_provider): /bus@10000000/pci@1a000000: '#interrupt-cells' found, but node is not an interrupt provider
    arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dtb: Warning (interrupt_map): Failed prerequisite 'interrupt_provider'
And a runtime warning introduced in commit 045b14ca5c36 ("of: WARN on
deprecated #address-cells/#size-cells handling"):
WARNING: CPU: 0 PID: 1 at drivers/of/base.c:106 of_bus_n_addr_cells+0x9c/0xe0
    Missing '#address-cells' in /bus@10000000/pci@1a000000/pci_bridge@9,0
The fix is similar to commit d89a415ff8d5 ("MIPS: Loongson64: DTS: Fix PCIe
port nodes for ls7a"), which has fixed the issue for ls2k (despite its
subject mentions ls7a).
Signed-off-by: Xi Ruoyao xry111@xry111.site
Signed-off-by: Thomas Bogendoerfer tsbogend@alpha.franken.de
Signed-off-by: Sasha Levin sashal@kernel.org
---
 arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 73 +++++++++++++++++++----
 1 file changed, 60 insertions(+), 13 deletions(-)

diff --git a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
index ed99ee316febb..1292e9ab282ad 100644
--- a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
+++ b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
@@ -63,7 +63,6 @@ pci@1a000000 {
    		device_type = "pci";
    		#address-cells = <3>;
    		#size-cells = <2>;
-			#interrupt-cells = <2>;
    		msi-parent = <&msi>;
reg = <0 0x1a000000 0 0x02000000>,
@@ -227,7 +226,7 @@ phy1: ethernet-phy@1 {
    			};
    		};
-			pci_bridge@9,0 {
+			pcie@9,0 {
    			compatible = "pci0014,7a19.1",
    					   "pci0014,7a19",
    					   "pciclass060400",
@@ -237,12 +236,16 @@ pci_bridge@9,0 {
    			interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;
    			interrupt-parent = <&pic>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				device_type = "pci";
    			#interrupt-cells = <1>;
    			interrupt-map-mask = <0 0 0 0>;
    			interrupt-map = <0 0 0 0 &pic 32 IRQ_TYPE_LEVEL_HIGH>;
+				ranges;
    		};
-			pci_bridge@a,0 {
+			pcie@a,0 {
    			compatible = "pci0014,7a09.1",
    					   "pci0014,7a09",
    					   "pciclass060400",
@@ -252,12 +255,16 @@ pci_bridge@a,0 {
    			interrupts = <33 IRQ_TYPE_LEVEL_HIGH>;
    			interrupt-parent = <&pic>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				device_type = "pci";
    			#interrupt-cells = <1>;
    			interrupt-map-mask = <0 0 0 0>;
    			interrupt-map = <0 0 0 0 &pic 33 IRQ_TYPE_LEVEL_HIGH>;
+				ranges;
    		};
-			pci_bridge@b,0 {
+			pcie@b,0 {
    			compatible = "pci0014,7a09.1",
    					   "pci0014,7a09",
    					   "pciclass060400",
@@ -267,12 +274,16 @@ pci_bridge@b,0 {
    			interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
    			interrupt-parent = <&pic>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				device_type = "pci";
    			#interrupt-cells = <1>;
    			interrupt-map-mask = <0 0 0 0>;
    			interrupt-map = <0 0 0 0 &pic 34 IRQ_TYPE_LEVEL_HIGH>;
+				ranges;
    		};
-			pci_bridge@c,0 {
+			pcie@c,0 {
    			compatible = "pci0014,7a09.1",
    					   "pci0014,7a09",
    					   "pciclass060400",
@@ -282,12 +293,16 @@ pci_bridge@c,0 {
    			interrupts = <35 IRQ_TYPE_LEVEL_HIGH>;
    			interrupt-parent = <&pic>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				device_type = "pci";
    			#interrupt-cells = <1>;
    			interrupt-map-mask = <0 0 0 0>;
    			interrupt-map = <0 0 0 0 &pic 35 IRQ_TYPE_LEVEL_HIGH>;
+				ranges;
    		};
-			pci_bridge@d,0 {
+			pcie@d,0 {
    			compatible = "pci0014,7a19.1",
    					   "pci0014,7a19",
    					   "pciclass060400",
@@ -297,12 +312,16 @@ pci_bridge@d,0 {
    			interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
    			interrupt-parent = <&pic>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				device_type = "pci";
    			#interrupt-cells = <1>;
    			interrupt-map-mask = <0 0 0 0>;
    			interrupt-map = <0 0 0 0 &pic 36 IRQ_TYPE_LEVEL_HIGH>;
+				ranges;
    		};
-			pci_bridge@e,0 {
+			pcie@e,0 {
    			compatible = "pci0014,7a09.1",
    					   "pci0014,7a09",
    					   "pciclass060400",
@@ -312,12 +331,16 @@ pci_bridge@e,0 {
    			interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
    			interrupt-parent = <&pic>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				device_type = "pci";
    			#interrupt-cells = <1>;
    			interrupt-map-mask = <0 0 0 0>;
    			interrupt-map = <0 0 0 0 &pic 37 IRQ_TYPE_LEVEL_HIGH>;
+				ranges;
    		};
-			pci_bridge@f,0 {
+			pcie@f,0 {
    			compatible = "pci0014,7a29.1",
    					   "pci0014,7a29",
    					   "pciclass060400",
@@ -327,12 +350,16 @@ pci_bridge@f,0 {
    			interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
    			interrupt-parent = <&pic>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				device_type = "pci";
    			#interrupt-cells = <1>;
    			interrupt-map-mask = <0 0 0 0>;
    			interrupt-map = <0 0 0 0 &pic 40 IRQ_TYPE_LEVEL_HIGH>;
+				ranges;
    		};
-			pci_bridge@10,0 {
+			pcie@10,0 {
    			compatible = "pci0014,7a19.1",
    					   "pci0014,7a19",
    					   "pciclass060400",
@@ -342,12 +369,16 @@ pci_bridge@10,0 {
    			interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
    			interrupt-parent = <&pic>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				device_type = "pci";
    			#interrupt-cells = <1>;
    			interrupt-map-mask = <0 0 0 0>;
    			interrupt-map = <0 0 0 0 &pic 41 IRQ_TYPE_LEVEL_HIGH>;
+				ranges;
    		};
-			pci_bridge@11,0 {
+			pcie@11,0 {
    			compatible = "pci0014,7a29.1",
    					   "pci0014,7a29",
    					   "pciclass060400",
@@ -357,12 +388,16 @@ pci_bridge@11,0 {
    			interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
    			interrupt-parent = <&pic>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				device_type = "pci";
    			#interrupt-cells = <1>;
    			interrupt-map-mask = <0 0 0 0>;
    			interrupt-map = <0 0 0 0 &pic 42 IRQ_TYPE_LEVEL_HIGH>;
+				ranges;
    		};
-			pci_bridge@12,0 {
+			pcie@12,0 {
    			compatible = "pci0014,7a19.1",
    					   "pci0014,7a19",
    					   "pciclass060400",
@@ -372,12 +407,16 @@ pci_bridge@12,0 {
    			interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
    			interrupt-parent = <&pic>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				device_type = "pci";
    			#interrupt-cells = <1>;
    			interrupt-map-mask = <0 0 0 0>;
    			interrupt-map = <0 0 0 0 &pic 43 IRQ_TYPE_LEVEL_HIGH>;
+				ranges;
    		};
-			pci_bridge@13,0 {
+			pcie@13,0 {
    			compatible = "pci0014,7a29.1",
    					   "pci0014,7a29",
    					   "pciclass060400",
@@ -387,12 +426,16 @@ pci_bridge@13,0 {
    			interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
    			interrupt-parent = <&pic>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				device_type = "pci";
    			#interrupt-cells = <1>;
    			interrupt-map-mask = <0 0 0 0>;
    			interrupt-map = <0 0 0 0 &pic 38 IRQ_TYPE_LEVEL_HIGH>;
+				ranges;
    		};
-			pci_bridge@14,0 {
+			pcie@14,0 {
    			compatible = "pci0014,7a19.1",
    					   "pci0014,7a19",
    					   "pciclass060400",
@@ -402,9 +445,13 @@ pci_bridge@14,0 {
    			interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
    			interrupt-parent = <&pic>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				device_type = "pci";
    			#interrupt-cells = <1>;
    			interrupt-map-mask = <0 0 0 0>;
    			interrupt-map = <0 0 0 0 &pic 39 IRQ_TYPE_LEVEL_HIGH>;
+				ranges;
    		};
    	};
-- 
2.43.0



    

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[PATCH AUTOSEL 5.15 4/5] MIPS: Loongson64: DTS: Really fix PCIe port nodes for ls7a