From: Geert Uytterhoeven geert+renesas@glider.be
[ Upstream commit 0a016639ef92b28eb74ba4fed21bee1f1328513a ]
When adding support for R-Car V3U, the Global FD Configuration register (CFDGFDCFG) and the Channel-specific CAN-FD Configuration Registers (CFDCmFDCFG) were mixed up. Use the correct register, and apply the selected CAN mode to all available channels.
Annotate the corresponding register bits, to make it clear they do not exist on older variants.
Fixes: 45721c406dcf50d4 ("can: rcar_canfd: Add support for r8a779a0 SoC") Signed-off-by: Geert Uytterhoeven geert+renesas@glider.be Link: https://lore.kernel.org/all/388ddf312917eb9f6cc460a481f68402a876f9b5.1674499... Signed-off-by: Marc Kleine-Budde mkl@pengutronix.de Signed-off-by: Sasha Levin sashal@kernel.org --- drivers/net/can/rcar/rcar_canfd.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/net/can/rcar/rcar_canfd.c b/drivers/net/can/rcar/rcar_canfd.c index f6fa7157b99b0..88de17d0bd79d 100644 --- a/drivers/net/can/rcar/rcar_canfd.c +++ b/drivers/net/can/rcar/rcar_canfd.c @@ -197,8 +197,8 @@ #define RCANFD_DCFG_DBRP(x) (((x) & 0xff) << 0)
/* RSCFDnCFDCmFDCFG */ -#define RCANFD_FDCFG_CLOE BIT(30) -#define RCANFD_FDCFG_FDOE BIT(28) +#define RCANFD_V3U_FDCFG_CLOE BIT(30) +#define RCANFD_V3U_FDCFG_FDOE BIT(28) #define RCANFD_FDCFG_TDCE BIT(9) #define RCANFD_FDCFG_TDCOC BIT(8) #define RCANFD_FDCFG_TDCO(x) (((x) & 0x7f) >> 16) @@ -429,8 +429,8 @@ #define RCANFD_C_RPGACC(r) (0x1900 + (0x04 * (r)))
/* R-Car V3U Classical and CAN FD mode specific register map */ -#define RCANFD_V3U_CFDCFG (0x1314) #define RCANFD_V3U_DCFG(m) (0x1400 + (0x20 * (m))) +#define RCANFD_V3U_FDCFG(m) (0x1404 + (0x20 * (m)))
#define RCANFD_V3U_GAFL_OFFSET (0x1800)
@@ -689,12 +689,13 @@ static void rcar_canfd_tx_failure_cleanup(struct net_device *ndev) static void rcar_canfd_set_mode(struct rcar_canfd_global *gpriv) { if (is_v3u(gpriv)) { - if (gpriv->fdmode) - rcar_canfd_set_bit(gpriv->base, RCANFD_V3U_CFDCFG, - RCANFD_FDCFG_FDOE); - else - rcar_canfd_set_bit(gpriv->base, RCANFD_V3U_CFDCFG, - RCANFD_FDCFG_CLOE); + u32 ch, val = gpriv->fdmode ? RCANFD_V3U_FDCFG_FDOE + : RCANFD_V3U_FDCFG_CLOE; + + for_each_set_bit(ch, &gpriv->channels_mask, + gpriv->info->max_channels) + rcar_canfd_set_bit(gpriv->base, RCANFD_V3U_FDCFG(ch), + val); } else { if (gpriv->fdmode) rcar_canfd_set_bit(gpriv->base, RCANFD_GRMCFG,