3.16.51-rc1 review patch. If anyone has any objections, please let me know.
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From: Matt Redfearn matt.redfearn@imgtec.com
commit 41885b02127c7ae169dc94542de4a8eed175495a upstream.
The stack unwinding code uses the mips_instuction union to decode the instructions it finds. That union uses the __BITFIELD_FIELD macro to reorder depending on endianness. The stack unwinding code always places 16bit instructions in halfword 1 of the union. This makes the union accesses correct for little endian systems. Similarly, 32bit instructions are reordered such that they are correct for little endian systems. This handling leaves unwinding the stack on big endian systems broken, as the mips_instruction union will then look for the fields in the wrong halfword.
To fix this, use a logical shift to place the 16bit instruction into the correct position in the word field of the union. Use the same shifting to order the 2 halfwords of 32bit instuctions. Then replace accesses to the halfword with accesses to the shifted word. In the case of the ADDIUS5 instruction, switch to using the mm16_r5_format union member to avoid the need for a 16bit shift.
Fixes: 34c2f668d0f6 ("MIPS: microMIPS: Add unaligned access support.") Signed-off-by: Matt Redfearn matt.redfearn@imgtec.com Reviewed-by: James Hogan james.hogan@imgtec.com Cc: Marcin Nowakowski marcin.nowakowski@imgtec.com Cc: Ingo Molnar mingo@kernel.org Cc: Paul Burton paul.burton@imgtec.com Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/16956/ Signed-off-by: Ralf Baechle ralf@linux-mips.org Signed-off-by: Ben Hutchings ben@decadent.org.uk --- arch/mips/kernel/process.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-)
--- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -235,7 +235,7 @@ static inline int is_ra_save_ins(union m * * microMIPS is way more fun... */ - if (mm_insn_16bit(ip->halfword[1])) { + if (mm_insn_16bit(ip->word >> 16)) { switch (ip->mm16_r5_format.opcode) { case mm_swsp16_op: if (ip->mm16_r5_format.rt != 31) @@ -314,7 +314,7 @@ static inline int is_jump_ins(union mips * * microMIPS is kind of more fun... */ - if (mm_insn_16bit(ip->halfword[1])) { + if (mm_insn_16bit(ip->word >> 16)) { if ((ip->mm16_r5_format.opcode == mm_pool16c_op && (ip->mm16_r5_format.rt & mm_jr16_op) == mm_jr16_op)) return 1; @@ -351,7 +351,7 @@ static inline int is_sp_move_ins(union m * * microMIPS is not more fun... */ - if (mm_insn_16bit(ip->halfword[1])) { + if (mm_insn_16bit(ip->word >> 16)) { return (ip->mm16_r3_format.opcode == mm_pool16d_op && ip->mm16_r3_format.simmediate & mm_addiusp_func) || (ip->mm16_r5_format.opcode == mm_pool16d_op && @@ -390,12 +390,10 @@ static int get_frame_info(struct mips_fr for (i = 0; i < max_insns && ip < ip_end; i++) { ip = (void *)ip + last_insn_size; if (is_mmips && mm_insn_16bit(ip->halfword[0])) { - insn.halfword[0] = 0; - insn.halfword[1] = ip->halfword[0]; + insn.word = ip->halfword[0] << 16; last_insn_size = 2; } else if (is_mmips) { - insn.halfword[0] = ip->halfword[1]; - insn.halfword[1] = ip->halfword[0]; + insn.word = ip->halfword[0] << 16 | ip->halfword[1]; last_insn_size = 4; } else { insn.word = ip->word; @@ -409,7 +407,7 @@ static int get_frame_info(struct mips_fr if (is_sp_move_ins(&insn)) { #ifdef CONFIG_CPU_MICROMIPS - if (mm_insn_16bit(ip->halfword[0])) + if (mm_insn_16bit(insn.word >> 16)) { unsigned short tmp;
@@ -422,7 +420,7 @@ static int get_frame_info(struct mips_fr tmp ^= 0x100; info->frame_size = -(signed short)(tmp << 2); } else { - tmp = (ip->halfword[0] >> 1); + tmp = (ip->mm16_r5_format.imm >> 1); info->frame_size = -(signed short)(tmp & 0xf); } } else