On 5/20/2025 2:07 AM, Krzysztof Kozlowski wrote:
On SM8750 the setting rate of pixel and byte clocks, while the parent DSI PHY PLL, fails with:
disp_cc_mdss_byte0_clk_src: rcg didn't update its configuration.
DSI PHY PLL has to be unprepared and its "PLL Power Down" bits in CMN_CTRL_0 asserted.
Mark these clocks with CLK_OPS_PARENT_ENABLE to ensure the parent is enabled during rate changes.
Cc: stable@vger.kernel.org Fixes: f1080d8dab0f ("clk: qcom: dispcc-sm8750: Add SM8750 Display clock controller") Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org
Changes in v6:
- Add CLK_OPS_PARENT_ENABLE also to pclk1, pclk2 and byte1.
- Add Fixes tag and cc-stable
Previously part of v5 (thus b4 diff might not work nice here): https://lore.kernel.org/r/20250430-b4-sm8750-display-v5-6-8cab30c3e4df@linar...
Changes in v5:
- New patch in above patchset.
Cc: Abhinav Kumar quic_abhinavk@quicinc.com Cc: Dmitry Baryshkov lumag@kernel.org
drivers/clk/qcom/dispcc-sm8750.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)
Reviewed-by: Abhinav Kumar quic_abhinavk@quicinc.com