-----Original Message----- From: Nautiyal, Ankit K ankit.k.nautiyal@intel.com Sent: Monday, August 2, 2021 6:27 PM To: intel-gfx@lists.freedesktop.org Cc: Shankar, Uma uma.shankar@intel.com; Zanoni, Paulo R paulo.r.zanoni@intel.com; ville.syrjala@linux.intel.com; daniel.vetter@ffwll.ch; jani.nikula@linux.intel.com; joonas.lahtinen@linux.intel.com; Vivi, Rodrigo rodrigo.vivi@intel.com; stable@vger.kernel.org Subject: [PATCH v2] drm/i915/display: Fix the 12 BPC bits for PIPE_MISC reg
From: Ankit Nautiyal ankit.k.nautiyal@intel.com
Till DISPLAY12 the PIPE_MISC bits 5-7 are used to set the Dithering BPC, with valid values of 6, 8, 10 BPC, with Dithering bit enabled. Also, these bits are used in case of HW readout for pipe_bpp in case of DSI. For ADLP+ these bits are used to set the PORT OUTPUT BPC, with valid values of: 6, 8, 10, 12 BPC, and need to be programmed whether dithering is enabled or not.
This patch: -corrects the bits 5-7 for PIPE MISC register for 12 BPC. -renames the bits and mask to have generic names for these bits for dithering bpc and port output bpc.
v2: Addressed the comments and suggestions from Uma Shankar: -Add 'display' in subject -Add Fixes tag in the commit message. -Take care of DSI case which uses the bits for getting pipe_bpp.
Fixes: 756f85cffef2 ("drm/i915/bdw: Broadwell has PIPEMISC") Cc: Paulo Zanoni paulo.r.zanoni@intel.com (v1) Cc: Ville Syrjälä ville.syrjala@linux.intel.com Cc: Daniel Vetter daniel.vetter@ffwll.ch Cc: Jani Nikula jani.nikula@linux.intel.com Cc: Joonas Lahtinen joonas.lahtinen@linux.intel.com Cc: Rodrigo Vivi rodrigo.vivi@intel.com Cc: intel-gfx@lists.freedesktop.org Cc: stable@vger.kernel.org # v3.13+
Signed-off-by: Ankit Nautiyal ankit.k.nautiyal@intel.com
drivers/gpu/drm/i915/display/intel_display.c | 18 +++++++++--------- drivers/gpu/drm/i915/i915_reg.h | 15 ++++++++++----- 2 files changed, 19 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 65ddb6c..9766b36 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5760,16 +5760,16 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
switch (crtc_state->pipe_bpp) { case 18:
val |= PIPEMISC_DITHER_6_BPC;
val |= PIPEMISC_6_BPC;
val |= PIPEMISC_DITHER_8_BPC;
val |= PIPEMISC_8_BPC;
val |= PIPEMISC_DITHER_10_BPC;
val |= PIPEMISC_10_BPC;
val |= PIPEMISC_DITHER_12_BPC;
val |= PIPEMISC_12_BPC;
Isn't this bit not supported on prior to Gen13 platforms, so from that perspective it's an Invalid operation. Can you confirm.
break;default: MISSING_CASE(crtc_state->pipe_bpp); @@ -5822,14 +5822,14 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
- switch (tmp & PIPEMISC_DITHER_BPC_MASK) {
- case PIPEMISC_DITHER_6_BPC:
- switch (tmp & PIPEMISC_BPC_MASK) {
- case PIPEMISC_6_BPC: return 18;
- case PIPEMISC_DITHER_8_BPC:
- case PIPEMISC_8_BPC: return 24;
- case PIPEMISC_DITHER_10_BPC:
- case PIPEMISC_10_BPC: return 30;
- case PIPEMISC_DITHER_12_BPC:
- case PIPEMISC_12_BPC: return 36;
Same here.
default: MISSING_CASE(tmp); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 943fe48..bbfe4f4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6166,11 +6166,16 @@ enum { #define PIPEMISC_HDR_MODE_PRECISION (1 << 23) /* icl+ */ #define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11) #define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */ -#define PIPEMISC_DITHER_BPC_MASK (7 << 5) -#define PIPEMISC_DITHER_8_BPC (0 << 5) -#define PIPEMISC_DITHER_10_BPC (1 << 5) -#define PIPEMISC_DITHER_6_BPC (2 << 5) -#define PIPEMISC_DITHER_12_BPC (3 << 5) +/*
- For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC.
- ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
- 6, 8, 10, 12 BPC.
- */
+#define PIPEMISC_BPC_MASK (7 << 5) +#define PIPEMISC_8_BPC (0 << 5) +#define PIPEMISC_10_BPC (1 << 5) +#define PIPEMISC_6_BPC (2 << 5) +#define PIPEMISC_12_BPC (4 << 5) /* adlp+ */ #define PIPEMISC_DITHER_ENABLE (1 << 4) #define PIPEMISC_DITHER_TYPE_MASK (3 << 2)
#define PIPEMISC_DITHER_TYPE_SP (0 << 2)
2.8.1