On Fri 01 Apr 06:33 PDT 2022, Johan Hovold wrote:
Commit ed8cc3b1fc84 ("PCI: qcom: Add support for SDM845 PCIe controller") introduced a clock imbalance by enabling the pipe clock both in init() and in post_init() but only disabling in post_deinit().
Note that the pipe clock was also never disabled in the init() error paths and that enabling the clock before powering up the PHY looks questionable.
Fixes: ed8cc3b1fc84 ("PCI: qcom: Add support for SDM845 PCIe controller") Cc: stable@vger.kernel.org # 5.6 Cc: Bjorn Andersson bjorn.andersson@linaro.org
Reviewed-by: Bjorn Andersson bjorn.andersson@linaro.org
Signed-off-by: Johan Hovold johan+linaro@kernel.org
Changes in v2
- Capitalise "Fix" in subject line according to PCI subsystem convention
drivers/pci/controller/dwc/pcie-qcom.c | 6 ------ 1 file changed, 6 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index b79d98e5e228..20a0e6533a1c 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1238,12 +1238,6 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) goto err_disable_clocks; }
- ret = clk_prepare_enable(res->pipe_clk);
- if (ret) {
dev_err(dev, "cannot prepare/enable pipe clock\n");goto err_disable_clocks;- }
- /* Wait for reset to complete, required on SM8450 */ usleep_range(1000, 1500);
2.35.1