From: Nicolas Ferre nicolas.ferre@microchip.com
[ Upstream commit 0c01fe49651d387776abed6a28541e80c8a93319 ]
Add a new word in assembly to store ACR value during the calls to at91_plla_disable/at91_plla_enable macros and use it.
Signed-off-by: Nicolas Ferre nicolas.ferre@microchip.com [cristian.birsan@microchip.com: remove ACR_DEFAULT_PLLA loading] Signed-off-by: Cristian Birsan cristian.birsan@microchip.com Link: https://lore.kernel.org/r/20250827145427.46819-4-nicolas.ferre@microchip.com Reviewed-by: Alexandre Belloni alexandre.belloni@bootlin.com Signed-off-by: Claudiu Beznea claudiu.beznea@tuxon.dev Signed-off-by: Sasha Levin sashal@kernel.org ---
LLM Generated explanations, may be completely bogus:
YES – the patch fixes a real suspend/resume regression on the SAM9X60-style PLLs and is safe to backport.
- `arch/arm/mach-at91/pm_suspend.S:693-767` now snapshots the PMC PLL Analog Control Register before disabling PLLA and restores that exact value when the PLL comes back up, instead of blindly reloading the legacy default `0x00020010`. Without this, every suspend cycle overwrote any board-/SoC-specific analog tuning done at boot, so PLLA resumed with the wrong charge-pump/loop-filter settings. - The saved word added at `arch/arm/mach-at91/pm_suspend.S:1214-1215` is the only state needed; no other logic changes are introduced. - Multiple SAM9X60-family clock descriptions (for example `drivers/clk/at91/sama7g5.c:110-126`, `drivers/clk/at91/sam9x60.c:39-52`) program PLL-specific `acr` values via `clk-sam9x60-pll.c`, and that driver explicitly writes those values into PMC_PLL_ACR before enabling the PLL (`drivers/clk/at91/clk-sam9x60-pll.c:106-134`). After suspend, the old code immediately replaced them with `AT91_PMC_PLL_ACR_DEFAULT_PLLA`, undoing the driver’s configuration and risking unlock or unstable clocks on affected boards. - The regression has existed since the original SAM9X60 PLL support (`4fd36e458392`), so every stable kernel that supports these SoCs can lose PLL configuration across low-power transitions. The fix is minimal, architecture-local, and does not alter behaviour on older PMC version 1 platforms because the new code is gated by both the PMC version check and `CONFIG_HAVE_AT91_SAM9X60_PLL`.
Given the clear bug fix, confined scope, and lack of risky side effects, this change fits the stable backport criteria. A good follow-up when backporting is to run a suspend/resume cycle on a SAM9X60/SAMA7 board to confirm PLL lock persists.
arch/arm/mach-at91/pm_suspend.S | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S index 7e6c94f8edeef..aad53ec9e957b 100644 --- a/arch/arm/mach-at91/pm_suspend.S +++ b/arch/arm/mach-at91/pm_suspend.S @@ -689,6 +689,10 @@ sr_dis_exit: bic tmp2, tmp2, #AT91_PMC_PLL_UPDT_ID str tmp2, [pmc, #AT91_PMC_PLL_UPDT]
+ /* save acr */ + ldr tmp2, [pmc, #AT91_PMC_PLL_ACR] + str tmp2, .saved_acr + /* save div. */ mov tmp1, #0 ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL0] @@ -758,7 +762,7 @@ sr_dis_exit: str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
/* step 2. */ - ldr tmp1, =AT91_PMC_PLL_ACR_DEFAULT_PLLA + ldr tmp1, .saved_acr str tmp1, [pmc, #AT91_PMC_PLL_ACR]
/* step 3. */ @@ -1207,6 +1211,8 @@ ENDPROC(at91_pm_suspend_in_sram) #endif .saved_mckr: .word 0 +.saved_acr: + .word 0 .saved_pllar: .word 0 .saved_sam9_lpr: