Re: [PATCH 1/2] drm/i915/gvt: Fix BDW command parser regression

On Wed, 14 Apr 2021, Zhenyu Wang wrote:

On BDW new Windows driver has brought extra registers to handle for LRM/LRR command in WA ctx. Add allowed registers in cmd parser for BDW.

Cc: Alex Williamson alex.williamson@redhat.com Cc: Yan Zhao yan.y.zhao@intel.com Cc: stable@vger.kernel.org Fixes: 73a37a43d1b0 ("drm/i915/gvt: filter cmds "lrr-src" and "lrr-dst" in cmd_handler") Signed-off-by: Zhenyu Wang zhenyuw@linux.intel.com

---

drivers/gpu/drm/i915/gvt/cmd_parser.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index fef1e857cefc..01c1d1b36acd 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -916,19 +916,26 @@ static int cmd_reg_handler(struct parser_exec_state *s,

if (!strncmp(cmd, "srm", 3) || !strncmp(cmd, "lrm", 3)) {

• if (offset != i915_mmio_reg_offset(GEN8_L3SQCREG4) &&
  

• 		offset != 0x21f0) {
  

• if (offset == i915_mmio_reg_offset(GEN8_L3SQCREG4) ||
  

•     offset == 0x21f0 ||
  

•     (IS_BROADWELL(gvt->gt->i915) &&
  

•      offset == i915_mmio_reg_offset(INSTPM)))
  

• 	return 0;
  

• else {
  gvt_vgpu_err("%s access to register (%x)\n",
  		cmd, offset);
  return -EPERM;
  

• } else
  

• 	return 0;
  

• }
  

  }

  if (!strncmp(cmd, "lrr-src", 7) || !strncmp(cmd, "lrr-dst", 7)) {

• gvt_vgpu_err("not allowed cmd %s\n", cmd);
  

• return -EPERM;
  

• if (IS_BROADWELL(gvt->gt->i915) && offset == 0x215c)
  

• 	return 0;
  

• else {
  

• 	gvt_vgpu_err("not allowed cmd %s reg (%x)\n", cmd, offset);
  

• 	return -EPERM;
  

• }
  

  }

  if (!strncmp(cmd, "pipe_ctrl", 9)) {

-- 2.31.0

---

intel-gvt-dev mailing list intel-gvt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev

Reviewed-by: Colin Xu colin.xu@intel.com

Thanks for the timely fix for BDW!